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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
    • PCIe Layering & TLPs
      • PCIe Layering & TLPs: Concepts
      • PCIe Layering & TLPs: Integration
      • PCIe Layering & TLPs: Debug
      • PCIe Layering & TLPs: Interview
    • Enumeration & Link Training
    • CXL Attach Modes
    • PCIe / CXL Debug
    • PCIe & CXL: Tricky Q&A
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←PCIe Layering & TLPs
  1. Topics
  2. Bus Protocols
  3. PCIe & CXL
  4. PCIe Layering & TLPs
  5. PCIe Layering & TLPs: Interview
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    Interface ProtocolsAll levels

    PCIe Layering & TLPs: Interview

    Interview for PCIe Layering & TLPs.

    Interview drills

    Why can a requester stop issuing reads while it still has free Tags and the link has request credits?

    Check yourself Why can a requester stop issuing reads while it still has free Tags and the link has request credits?

    Its local completion-data reservation can be exhausted. Tags, link credits and destination storage are separate admission resources.

    Common trap: Giving a generic fix without identifying the boundary and unmet obligation in this example.

    What do PCIe credits control?

    Check yourself What do PCIe credits control?

    They advertise receiver header/data buffering for Posted, Non-Posted and Completion traffic in a virtual channel. A transmitter may send a TLP only when the required credit units are available; the six accounting classes are not one count of arbitrary TLPs. Lack of a required credit backpressures that traffic until an update or other specified event.

    Common trap: Confusing credits with link width.

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    See also

    • PCIe Layering & TLPs: Concepts
    • PCIe Layering & TLPs: Integration