AXI AW / W / B / AR / R

Write address, write data, write response, read address and read data channels, each with its own handshake and payload. R includes read status; a read has no separate B response.

Offer / acceptance

An offer presents pending work. On the AXI-style channels here, acceptance occurs at a sampled edge with VALID && READY; either signal alone is insufficient.

Beat / burst

A data beat is one channel transfer unit. A burst associates one request with its specified number of beats; count accepted beats, not waiting cycles.

Payload retention

A stalled AXI offer retains VALID and its full channel payload through the accepting edge, outside reset. A different protocol may define another contract.

Backpressure / skid storage

Backpressure slows upstream acceptance. A skid slot retains an extra accepted item during delayed stop propagation; the output's stalled offer remains intact.

Occupancy / stop latency

Occupancy is initial items plus accepted arrivals minus completed departures. Stop latency allows further arrivals before backpressure takes effect.

Outstanding / completion

Accepted work whose protocol-defined completion obligation remains. State whether the boundary is a channel beat, complete response, target side effect or software notification.

ID / Tag / correlation context

An interface identity can be reused or remapped. Retain observed port, ordering stream, sequence and stored request fields; responses need not carry the original address.

Same-ID order

Ordinary AXI4 reads preserve request order within one observed port/ARID; writes have a separate AWID/B stream. Equal R/B numeric IDs do not combine them.

Coherence / consistency

Coherence concerns values and permissions per location. A memory model constrains combinations of observations across operations; one does not establish the other.

Barrier / fence / publication

Architecture, language/OS and device contracts define ordering and visibility. A fence is not universally a cache flush or proof that a device finished its work.

Throughput / payload efficiency

Throughput is useful accepted bytes per elapsed time. Payload efficiency is useful payload divided by transmitted bytes at a stated boundary; idle time needs separate accounting.

Tail latency / head-of-line blocking

Name admission/completion timestamps and report the required percentile. Head-of-line blocking occurs when a blocked queue head prevents otherwise serviceable later work.

Little's Law

For a stable population at one boundary, average in-flight work equals completion rate times average residence time. This is not a worst-case FIFO-depth bound.

Transfer size / byte lane / strobe

Address and size select a transfer window; enabled write strobes select bytes within it. Physical bus width alone does not specify all bytes written.

AxLEN / AxSIZE / LAST

For the ordinary AXI4 bursts here, AxLEN encodes beats minus one and AxSIZE the power-of-two byte size per transfer. WLAST/RLAST identify final data beats under their respective handshake rules.

Stream TKEEP / TLAST

In the scoped AXI4-Stream example, TKEEP identifies valid byte lanes and TLAST the final packet beat. Both belong to the retained offered payload during a stall.

APB SETUP / ACCESS

SETUP has PSEL=1, PENABLE=0. ACCESS has both high; completion needs PREADY at its sampled edge. Waited ACCESS cycles are not extra writes.

AHB address / data phase

An accepted address controls a later data phase. Save its context; the currently visible address may belong to different work.

DECERR / SLVERR

In the course model an unmapped AXI address reaches a default target returning DECERR. A completed APB target error maps upstream to SLVERR. Waiting is not either error.

CDC / reset epoch

Clock-domain crossing preserves the transaction contract across clocks. An epoch identifies observer/recovery context after reset; it is not an invented AXI R field.

Cancellation policy

Drain, retain, cancel or isolate pending work according to an explicit system policy. AXI handshake rules alone do not select one universal mid-transaction reset policy.

MESI / dirty responsibility

MESI stable states describe valid permissions and dirty data responsibility in an abstract protocol. ACE has its own state/response semantics; do not equate their letters automatically.

ACE AC / CR / CD / RACK

AC requests a peer snoop, CR reports its result, CD carries required peer data. The requester receives read data on R and provides the defined read acknowledgement RACK.

Shareability / DVM

Shareability helps define participation for an access. ACE DVM carries defined virtual-memory maintenance/synchronisation messages; it is not a generic data-cache flush.

PoC / PoU

Point of Coherency and Point of Unification name architecture-defined maintenance scopes. Select the required operation, target point and completion sequence from the platform contract.

CHI REQ / RSP / DAT / SNP

Request, response, data and snoop message roles. Node capability, resources and dependency rules still matter; separate classes do not prove progress.

Protocol Credit / link credit

CHI RetryAck and a suitable PCrdGrant govern a credited retry. Link flow control and implementation-specific NoC buffers are distinct resources.

Deadlock / livelock / starvation

Deadlock requires a persistent resource-dependency cycle under stated assumptions. Livelock is activity without useful completion; starvation denies one eligible participant while others may progress.

Controller / PHY / DFI

The controller schedules memory commands; the PHY implements the selected signalling/timing interface. DFI is their separately versioned interface, not the external DRAM specification.

Row hit / idle bank / row conflict

A hit accesses the active row. An idle bank needs ACTIVATE; a conflict needs legal PRECHARGE and ACTIVATE before the new row access.

tRP / tRCD

Selected-device minimum precharge-to-activate and activate-to-column timing relationships. Other timing constraints still apply; these two alone do not specify full read latency.

tREFI / tRFC

tREFI describes average refresh-command spacing; tRFC is refresh recovery. Neither is the entire refresh window. Limits depend on device, mode and conditions.

Write levelling / read capture

DDR3/DDR4 write levelling relates write DQS to DRAM CK. Read capture and data centring concern other relationships; one pass does not establish every margin.

CK / DQ / DQS

DRAM clock, data signals and data strobe. Identify which relationship a training result measures rather than calling every calibration the same eye-centre search.

MT/s / clock rate

MT/s counts million transfers per second. It is not automatically MHz; do not multiply a DDR transfer-rate rating by two a second time.

ECC / FCS

ECC reports refer to the platform's protected data and recovery contract. Ethernet FCS checks frame integrity at its observation point. Neither report alone locates the physical cause.

TLP / DLLP / LTSSM

In conventional non-Flit PCIe, TLPs carry transactions, DLLPs include hop-local link control, and LTSSM history describes link training/state. A link ACK is not a Memory Read Completion.

BAR / DMA address

A BAR exposes an endpoint aperture to the host. A host-directed device DMA operation uses a valid platform DMA mapping, which need not be a CPU pointer or inside that BAR.

CXL.io / .cache / .mem

In the scoped CXL 2.0 type model: .io serves discovery/configuration/I/O, .cache supports device caching of host memory, and .mem host access to device memory. Device type and configuration matter.

I²C ACK / NACK

The ninth clock reports acknowledgement by the receiver for that phase. A controller's intentional NACK on the last read byte differs from an address NACK.

SPI CPOL / CPHA

Conventional mode names specify idle polarity and leading/trailing sampling edge. The target separately defines CS timing, word order and command framing.

UART 8N1 / flow control

One start, eight data, no parity and one stop occupy ten bit periods. FIFO headroom must cover worst-case service and in-flight characters under the selected RTS/CTS or software contract.

USB token / endpoint / toggle

In the USB 2.0 examples, the host schedules endpoint transactions. Bulk NAK accepts no payload; DATA0/DATA1 progression follows the applicable successful-transaction rules.

MAC / PCS / PHY

The MAC handles Ethernet frames. PCS is a physical sublayer within the selected PHY architecture; encoding, FEC and medium attachment vary by mode.

CSI-2 / DSI / D-PHY

CSI-2 camera packets and DSI display operation are separate protocols. D-PHY is a physical mapping; the conventional forwarded-clock sketch is not a C-PHY diagram.

VIP / active / passive

VIP provides configured protocol stimulus/observation/checking. Active owns assigned stimulus; passive observes. Block versus chip level does not alone choose the role.

Assertion / scoreboard / oracle

Assertions express precisely sampled obligations. Scoreboards correlate observed work against stored expectations; an oracle supplies independent expected results. Their scopes can overlap.

Coverage / waiver / evidence gap

Coverage records included scenarios observed. A waiver records reviewed scope/risk disposition. Neither replaces correctness evidence for an applicable requirement.

Positive control / mutation / repaired replay

A positive control must preserve legal behaviour. A mutation tests detection of a known fault. A clean replay checks the restored baseline; it is not automatic validation of a separately edited patch.

Harness PASS / non-vacuity

A fault-detection harness passes when its expected rejection and clean controls hold with actual observed work. That does not mean the faulty selection is compliant or the entire system verified.