Context → boundaries → first observed divergence → discriminator → regression.
Interface | Evidence to keep together |
|---|---|
AMBA | Accepted AR/AW/W/R/B items, source/ID context, bursts and responses |
ACE / CHI | Line state, home/snoop obligations, shareability and retry context |
DDR | Controller/PHY configuration, training, command timing, refresh and errors |
PCIe / CXL | Packet/Tag context, link state, credits, mappings and attach capabilities |
Peripheral | Reset state, register contract, interrupt source and DMA ownership |
Verification | Monitor events, independent expectations, assertions, coverage and requirement evidence |
Observation | What remains to establish |
|---|---|
Sequence item submitted | Actual hardware acceptance and result. |
AXI AW or W accepted | Other required parts, target work and response obligations. |
APB SETUP or waiting ACCESS | The completing ACCESS edge and response status. |
PCIe link ACK | The Memory Read's transaction-level Completion/data. |
IRQ controller acknowledged | The peripheral source's documented deassertion and event handling. |
Harness PASS | Whether the result is a clean control or expected mutation rejection, and what remains unverified. |
Shared model and trace conventions
Definitions with worked-lesson links
Which transaction failed first?
Which layer owns forward progress?
Is the observed behavior illegal or merely unexpected?
Which metric demonstrates the stated product impact?
Which evidence distinguishes the leading root-cause hypotheses?
Which regression protects compatibility?