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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
    • PCIe Layering & TLPs
      • PCIe Layering & TLPs: Concepts
      • PCIe Layering & TLPs: Integration
      • PCIe Layering & TLPs: Debug
      • PCIe Layering & TLPs: Interview
    • Enumeration & Link Training
    • CXL Attach Modes
    • PCIe / CXL Debug
    • PCIe & CXL: Tricky Q&A
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←PCIe Layering & TLPs
  1. Topics
  2. Bus Protocols
  3. PCIe & CXL
  4. PCIe Layering & TLPs
  5. PCIe Layering & TLPs: Concepts
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    Interface ProtocolsAll levels

    PCIe Layering & TLPs: Concepts

    Concepts for PCIe Layering & TLPs.

    Core concepts

    Read a TLP by the job it asks the receiver to do

    For the conventional PCIe 5.0 non-Flit scope, a posted Memory Write carries data without a transaction-layer Completion. A Memory Read is non-posted and returns data through Completion TLPs; configuration requests also need Completions. A link ACK is different: it concerns hop-level reception/replay, not whether the requested read or register action has completed.

    Read a header in this order: format/type, length, request identity and address or completion status. A request’s Requester ID and Tag correlate the eventual Completion; read Completions can divide the returned data into multiple packets. Address width determines the applicable request-header format. This survey does not invent bit positions or use a Memory Read’s field layout for Completion headers.

    Read a TLP by the job it asks the receiver to do — worked trace

    Illustrative isolated example; not measured silicon behaviour.

    Packet role

    Fields to inspect

    State to retain

    Memory Read request

    Requester ID, Tag, address, length, byte enables

    Destination buffer, requested byte range and unfinished bytes

    Completion with Data

    Completer/status plus requester/tag and returned-range information

    Match to outstanding request; account for all expected bytes

    Posted Memory Write

    Address, length, byte enables, payload

    Link delivery is not a per-write Completion TLP

    Link ACK

    Link sequence context

    Replay progress only, not application success

    Check yourself A Memory Read receives a link ACK but no Completion. May its Tag be reused immediately?

    No. The read remains outstanding at the transaction layer. The ACK does not supply its data or retire its completion obligation.

    Three layers

    Read first: Outstanding work and response identity

    Read first: Specialist PCIe/CXL course for deeper transaction and link study

    Scope: conventional non-Flit PCIe through the PCI Express Base Specification Revision 5.0 model. The examples below do not describe PCIe 6.0 Flit-mode framing, FEC or shared flow control. They are transaction surveys, not a compliance checklist. CXL is scoped separately to Revision 2.0 Version 1.0 in its attach-mode lesson.

    Transaction Layer (TL): TLPs carry the actual request — memory read/write, config access, message. Each TLP has a header (type, length, address/requester ID) and optional payload.

    For the conventional non-Flit PCIe examples in this overview, the Data Link Layer uses sequence numbers, link CRC and ACK/NAK with replay of unacknowledged TLPs. Link retry improves delivery reliability within its supported conditions; it is not a guarantee against every persistent fault. Newer Flit-mode mechanisms require their own revision-specific treatment.

    The Physical Layer handles link training, lanes and electrical signalling. PCIe Gen1/Gen2 use 8b/10b; Gen3–Gen5 use 128b/130b. Do not extend this encoding summary to every later generation.

    Follow one request through distinct PCIe obligations

    Conventional non-Flit PCIe scope already named in the lesson; these are layer responsibilities rather than a full packet layout.

    View

    Example evidence

    Still separate

    Software / application

    Mapped buffer or register operation

    Actual packet admission and completion

    Transaction

    Memory Read request and matching Completion data

    Per-link replay bookkeeping

    Data link

    Sequence, link CRC, ACK/NAK and replay

    Completion of the end-to-end Memory Read

    Physical

    Training, lanes and selected encoding

    Correct address, request identity and returned bytes

    What to notice

    • A link ACK concerns hop-level reception, while Completion data satisfies transaction work.

    • A healthy physical link does not validate the software mapping or transaction payload.

    Check yourself A link ACK is present but the read data never returns. Which row still has unfinished work?

    The transaction row. Its Memory Read Completion/data obligation is not discharged by the link ACK.

    A successful one-DWORD Memory Read

    Illustrative endpoint E reads four bytes from a valid host DMA mapping A using an available Tag 3. Assume no reset, poison or error, a supported request size, correct enables/permissions and enough receive capacity. The host returns one successful Completion with Data (CplD); larger requests can need multiple completions.

    Milestone

    Identity / route

    Still outstanding

    E sends MemRd(A)

    Requester ID E + Tag 3; request address-routed

    Four bytes and a successful transaction result.

    Adjacent link ACKs request

    Hop-local link sequence

    The same four bytes: ACK is not the Memory Read's Completion.

    Host services A

    Mapping and permissions select host memory

    Return CplD towards Requester ID E.

    E receives CplD

    Match Requester ID + Tag, status, byte count and address context

    Retire only once all expected data/status obligations are satisfied.

    Check yourself The request was ACKed by the adjacent switch, but no CplD arrived. Is the read finished?

    No. The ACK concerns link delivery on that hop. The Memory Read remains outstanding until its required transaction-level completion is received or an error/timeout recovery policy resolves it. A posted Memory Write has different semantics and does not receive a normal transaction Completion.

    Credits and flow control

    PCIe flow control accounts for Posted, Non-Posted and Completion header/data resources per virtual channel. A finite-credit transmitter must have every required class available before sending that TLP; unused Posted credits cannot pay for a Non-Posted request. Interpret infinite-credit encodings according to the selected port/revision instead of treating them as finite counters.

    Request flow-control credits, requester Tags and space reserved for returning completions are different resources. Conventional endpoints advertise infinite Completion credits as receivers and must limit requests so returning completions can be absorbed. Do not diagnose endpoint read stalls by assuming its advertised Completion credits count down to zero; inspect local receive reservations, Tags and the relevant finite-credit links separately.

    Which resource can block this read?

    Resource observation

    Effect

    What it does not establish

    Non-Posted header credit unavailable on a finite-credit link

    MemRd cannot be transmitted on that link yet

    Posted write credits do not unblock it.

    No free requester Tag

    Requester cannot allocate another live read identity

    Healthy link credits do not create a Tag.

    Local completion receive reservation unavailable

    Endpoint must throttle new reads to protect returning data

    Infinite advertised Completion credit does not mean unlimited physical storage.

    Remote service delayed

    An admitted read waits for service/return traffic

    A quiet request transmitter alone does not locate the delay.

    Check yourself All link credit indicators look healthy but E has no free Tags. Should increasing link width admit another read?

    Not by itself. E first needs a legal free request identity and receive reservation. Diagnose request admission, link transmission and completion return as separate stages; width is not a substitute for either resource.

    • Track Posted, Non-Posted and Completion traffic with their header/data credit accounting for the selected virtual channel; one scalar TLP count is not a complete credit model.

    • Credit update uses DLLPs — not visible as TLPs.

    • Switch ports have independent credit pools per direction.

    Apply the mechanism

    Continue to the integration exercise

    Then trace a failure

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    See also

    • PCIe Layering & TLPs: Debug
    • PCIe Layering & TLPs: Interview