Agents / IDs

CPU0 and DMA0 are AXI4 managers. CPU0 normally uses ID 1; DMA0 uses repeated ID 3 and optional independent ID 7. Preserve source-port/ID/sequence context internally.

AXI

64-bit data, 32-bit byte addresses, four-bit IDs; ordinary INCR examples unless explicitly scoped otherwise.

SRAM0

0x2000_0000–0x2000_FFFF; initially zero except where a lesson explicitly initialises read-only words.

APB_BRIDGE

32-bit APB window 0x4000_0000–0x4000_FFFF, with protocol-aware finite asynchronous request/response crossing. Capacity and service are stated per exercise.

DMA_CFG

SRC 0x4000_0000; DST ...0004; LEN_BYTES ...0008; CONTROL ...000C (START bit 0); STATUS ...0010 (DONE bit 0, BUSY bit 1); IRQ_STATUS ...0014 (DONE bit 0, W1C).

PERIPH0_TX

0x4000_0100; four 32-bit FIFO entries, accepted on completing APB transfers; consumption and level-IRQ condition are exercise-specific.

Clocks

clk_sys=100 MHz; clk_per=50 MHz. Never infer a fixed cross-domain edge offset from those rates alone.

Reset

Base examples start quiescent with both domains ready; active-low reset assertion is asynchronous and release is synchronised in each domain. A reset-during-traffic lesson states its own recovery policy.

Errors

Unmapped AXI default target returns DECERR; completed APB PSLVERR maps to SLVERR. Neither response is implied by backpressure alone.

Trace notation

En denotes a sampled edge in its named domain; post-edge state is labelled. Causal milestone tables and hand-authored sketches are not simulation waveforms.