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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
    • APB & AHB Basics
    • AXI Channels & Transfers
    • AXI-Lite & AXI-Stream
    • AMBA Integration Debug
    • AMBA Family (APB / AHB / AXI): Tricky Q&A
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Bus Protocols
  1. Topics
  2. Bus Protocols
  3. AMBA Family (APB / AHB / AXI)
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    Interface ProtocolsAll levels

    AMBA Family (APB / AHB / AXI)

    APB register access, AHB bursts, AXI channels, AXI-Lite, AXI-Stream, bridges, interconnect, and integration pitfalls.

    • 5topics
    • 17lessons

    Section overview

    APB register access, AHB bursts, AXI channels, AXI-Lite, AXI-Stream, bridges, interconnect, and integration pitfalls.

    Topics

    1. APB & AHB Basics

    2. AXI Channels & Transfers

    3. AXI-Lite & AXI-Stream

    4. AMBA Integration Debug

    Related topics

    • Protocols course hub

    After this section

    Try the section checkpoint, then review the Q&A

    Section context

    AMBA interfaces cover different contracts: APB's setup/access transfers, AHB's pipelined bus model, and AXI's independent channels and outstanding transactions.

    Illustrative review scenario

    Illustrative review: W arrived before AW, which is legal AXI4 traffic, but a converter neither buffered the early data nor backpressured it. The defect was the converter's admission contract, not channel arrival order.

    PreviousNext: APB & AHB Basics

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    Up nextAPB & AHB Basics

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    See also

    • How to Use This Course
    • Protocol Metrics Reference
    • Protocols Glossary