Controller/PHY split, training, timing modes, refresh, bank conflicts, bandwidth efficiency, and memory subsystem debug.
Try the section checkpoint, then review the Q&A
DDR bandwidth is scheduler + PHY: rows, banks, refresh, and turnarounds eat headline data rate.
Illustrative review: a video replay's long-run bandwidth looked sufficient, but a measured service gap overflowed its ingress buffer. Controller events, arbitration, backpressure and low-power/refresh state remained hypotheses until correlated on one timeline.