Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
    • PCIe Layering & TLPs
    • Enumeration & Link Training
      • Enumeration & Link Training: Concepts
      • Enumeration & Link Training: Integration
      • Enumeration & Link Training: Debug
      • Enumeration & Link Training: Interview
    • CXL Attach Modes
    • PCIe / CXL Debug
    • PCIe & CXL: Tricky Q&A
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
Loading lesson

←PCIe & CXL
  1. Topics
  2. Bus Protocols
  3. PCIe & CXL
  4. Enumeration & Link Training
On this page

    Interface ProtocolsAll levels

    Enumeration & Link Training

    Link training enables communication; enumeration and driver setup establish resources for normal device use. Configuration traffic is part of that setup.

    • 4topics
    • 4lessons

    What you'll learn

    Link training enables communication; enumeration and driver setup establish resources for normal device use. Configuration traffic is part of that setup.

    • LTSSM: Detect → Polling → Configuration → L0.

    • Link training establishes the link's speed and width using lane-level training evidence.

    • Enumeration assigns bus numbers, BARs, and capabilities.

    Connection

    Bring-up survey: connect link establishment to configuration access, resource assignment and driver readiness. Margin and configured capability both matter.


    Key diagram

    L0 is before usable device resources

    L0 is before usable device resources. Successful bring-up milestones, not the complete LTSSM or a universal OS implementation order. Configuration traffic itself uses the link before normal operation.
    Successful bring-up milestones, not the complete LTSSM or a universal OS implementation order. Configuration traffic itself uses the link before normal operation.
    Check yourself Does reaching L0 prove that the driver can safely use device registers and DMA?

    No. Discovery, resource assignment, enabling/mapping and the applicable DMA/interrupt setup are still required.


    Study this topic

    1. Concepts — rules and mental models

    2. Integration — system contracts

    3. Debug — trace the first divergence

    4. Interview — explain and defend your answer

    PreviousNext: Enumeration & Link Training: Concepts

    Up next

    Up nextEnumeration & Link Training: Concepts

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • PCIe Layering & TLPs
    • CXL Attach Modes
    • PCIe / CXL Debug