CXL adds cache coherency and memory semantics on top of PCIe physical layer.
4topics
4lessons
What you'll learn
CXL adds cache coherency and memory semantics on top of PCIe physical layer.
CXL.io: standard PCIe transactions for discovery and config.
CXL.cache: device caches host memory coherently.
CXL.mem: host accesses device-attached memory.
Connection
Extends PCIe layering with coherence concepts from ACE/CHI section.
Key diagram
CXL 2.0 roles are different paths
CXL 2.0 roles are different paths. CXL 2.0 Version 1.0 type model. All three types use .io; the lower edges show their additional .cache/.mem roles, not physical packet routes.
CXL 2.0 Version 1.0 type model. All three types use .io; the lower edges show their additional .cache/.mem roles, not physical packet routes. Check yourselfWhich additional path must not be inferred from discovering a Type 3 device?
CXL.cache. The scoped Type 3 role uses .io and .mem, without device caching of host memory through .cache.