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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
    • PCIe Layering & TLPs
      • PCIe Layering & TLPs: Concepts
      • PCIe Layering & TLPs: Integration
      • PCIe Layering & TLPs: Debug
      • PCIe Layering & TLPs: Interview
    • Enumeration & Link Training
    • CXL Attach Modes
    • PCIe / CXL Debug
    • PCIe & CXL: Tricky Q&A
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←PCIe & CXL
  1. Topics
  2. Bus Protocols
  3. PCIe & CXL
  4. PCIe Layering & TLPs
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    Interface ProtocolsAll levels

    PCIe Layering & TLPs

    PCIe delivers reliable packets over unreliable links — three layers, each with distinct failure modes.

    • 4topics
    • 4lessons

    What you'll learn

    PCIe delivers reliable packets over unreliable links — three layers, each with distinct failure modes.

    • Transaction layer: TLPs (Memory Read/Write, Config, Completion).

    • Data link layer: DLLPs, ACK/NAK, replay buffer.

    • Physical layer: LTSSM, lanes, encoding, equalization.

    Connection

    Applies layering model from fundamentals to chip-to-chip interconnect.


    Key diagram

    Link ACK does not complete a Memory Read

    Link ACK does not complete a Memory Read. Conventional non-Flit PCIe scope. A read's transaction obligation survives hop-level acknowledgement and can involve more than one Completion packet.
    Conventional non-Flit PCIe scope. A read's transaction obligation survives hop-level acknowledgement and can involve more than one Completion packet.
    Check yourself Which branch supplies the requested read bytes?

    The Completion-with-Data branch, not the link ACK branch.


    Study this topic

    1. Concepts — rules and mental models

    2. Integration — system contracts

    3. Debug — trace the first divergence

    4. Interview — explain and defend your answer

    PreviousNext: PCIe Layering & TLPs: Concepts

    Up next

    Up nextPCIe Layering & TLPs: Concepts

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    See also

    • Enumeration & Link Training
    • CXL Attach Modes
    • PCIe / CXL Debug