Identify which operation, address space and resource a link observation actually covers.
Try these before opening the explanations. This is a self-assessment, not a stored score or certification.
No. ACK is hop-local delivery evidence, not the read Completion. Tags and local return-data reservation can limit request admission even with healthy flow-control credits. Apply finite/infinite credit rules for the actual port.
Neither. This type supplies .io and .mem in the scoped model, not .cache. Exposing memory does not create the application's ordering, ownership or synchronisation contract.
Ready to continue when you can produce:
One Memory Read's Requester ID/Tag and transaction-level completion evidence.
Separate CPU BAR access, host-directed DMA mapping and the selected CXL protocol/type.
They advertise receiver buffering in header and data credit units for Posted, Non-Posted and Completion traffic. A transmitter checks the credits required by a TLP before sending it; a credit count is not simply a count of arbitrary TLPs.
Common trap: Confusing credits with link width or collapsing six accounting classes into one counter.
Confirm the negotiated versus expected width/speed, then inspect LTSSM history, lane status, configuration, disabled/degraded-lane policy, endpoint capability and physical margin evidence. L0 alone does not identify SI, packaging or firmware as the cause.
Common trap: Assigning ownership from the final LTSSM state without the negotiation and lane history.
In the scoped CXL 2.0 model, .cache lets a participating device cache host memory, while .mem provides host access to configured device-attached memory. Type 1 has .io/.cache, Type 2 all three and Type 3 .io/.mem. A working .io path does not establish other protocol enablement, memory exposure or software synchronisation.
Common trap: Treating all CXL as PCIe DMA or inferring .cache from Type 3 enumeration.