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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Bus Protocols
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
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    Interface ProtocolsAll levels

    High-Speed I/O (USB / Ethernet / MIPI)

    Link bring-up, packet framing, lane training, PHY/digital split, MAC/PCS boundaries, and system-level bandwidth planning.

    • 5topics
    • 17lessons

    Section overview

    Link bring-up, packet framing, lane training, PHY/digital split, MAC/PCS boundaries, and system-level bandwidth planning.

    Topics

    1. USB Link & Packet Model

    2. Ethernet MAC / PHY Basics

    3. MIPI CSI / DSI Overview

    4. High-Speed I/O Debug

    Related topics

    • Protocols course hub

    After this section

    Try the section checkpoint, then review the Q&A

    Section context

    USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

    Illustrative review scenario

    Illustrative review: a product-board link showed FCS errors and one lane's measured margin differed from the eval board. Configuration, lane mapping, clocks and channel evidence were compared before the package path was accepted as the discriminator.

    PreviousNext: USB Link & Packet Model

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    Up nextUSB Link & Packet Model

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    See also

    • How to Use This Course
    • Protocol Metrics Reference
    • Protocols Glossary