PCIe transaction, data-link, and physical layers; enumeration; link training; credits; CXL attach modes; and performance tuning.
Try the section checkpoint, then review the Q&A
PCIe/CXL debug correlates link history, credit/resource state, routed requests/completions and software mappings for the same operation; no fixed layer order identifies ownership by itself.
Illustrative review: an endpoint enumerated but one DMA read timed out. The team compared Non-Posted and Completion credits, requester/tag routing, DMA mapping and returned completions before assigning a switch, endpoint or software cause.