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Interface ProtocolsAll levels

Core path: follow one operation from request to completion

Read the Concepts pages in this order, then use each topic's Integration and Debug pages. The core teaches local acceptance, transaction identity, useful bytes, bus timing and end-to-end evidence. The other interface sections remain available as survey branches.

Step	Lesson	What it contributes
1	Layering & Transaction Model	Define the operation and the observation boundary.
2	Handshake & Backpressure	Separate offered work, accepted work and retained storage.
3	Ordering & Outstanding Rules	Keep request identity and permitted response order.
4	Bandwidth & Latency Budgeting	Measure useful accepted bytes and resource limits.
5	APB & AHB Basics	Trace APB phases and AHB-Lite pipeline association.
6	AXI Channels & Transfers	Combine channel timing with byte lanes, burst limits and IDs.
7	AXI-Lite & AXI-Stream	Apply register-write retention and packet-byte preservation.
8	AMBA Integration & Debug	Carry one operation through conversion, crossings and errors.
9	Scoreboard & Checker Strategy	Choose checks that observe the intended failure.

Check yourself Can you trace CPU0's LEN_BYTES write without treating AXI acceptance, APB completion and B acceptance as one event?

Follow the enabled four bytes at the upstream interface, the retained bridge command, the completing APB access and the restored BID/B response. Revisit the bridge walkthrough if any boundary or pending state is missing.

Finish the core path with the blind Bus Integration Lab

Optional survey branches

Complete the core and lab without reading every survey first. Choose the branch required by your role; each survey is an entry point, not implementation or compliance training.

Branch	Read first	Entry lesson
Coherence	AXI channels; stable cache permissions	States, ownership and maintenance
Memory	Acceptance, queues and bandwidth units	Controller and PHY
PCIe/CXL	Layering, request identity and resources	Requests, links and completions
Peripherals	Register access and sampled events	Serial timing and acknowledgements
High-speed I/O	Layers, payload rates and finite buffering	USB transfer model

By role

RTL owner: fundamentals → AMBA → memory interfaces → debug pages.
Verification owner: fundamentals → protocol verification → AMBA/coherence.
SoC architect: fundamentals → bandwidth budgeting → coherence → PCIe/CXL.
Bring-up engineer: memory interfaces → PCIe/CXL → high-speed I/O → debug.

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Core path: follow one operation from request to completion

Step	Lesson	What it contributes
1	Layering & Transaction Model	Define the operation and the observation boundary.
2	Handshake & Backpressure	Separate offered work, accepted work and retained storage.
3	Ordering & Outstanding Rules	Keep request identity and permitted response order.
4	Bandwidth & Latency Budgeting	Measure useful accepted bytes and resource limits.
5	APB & AHB Basics	Trace APB phases and AHB-Lite pipeline association.
6	AXI Channels & Transfers	Combine channel timing with byte lanes, burst limits and IDs.
7	AXI-Lite & AXI-Stream	Apply register-write retention and packet-byte preservation.
8	AMBA Integration & Debug	Carry one operation through conversion, crossings and errors.
9	Scoreboard & Checker Strategy	Choose checks that observe the intended failure.

Check yourself Can you trace CPU0's LEN_BYTES write without treating AXI acceptance, APB completion and B acceptance as one event?

Optional survey branches

Complete the core and lab without reading every survey first. Choose the branch required by your role; each survey is an entry point, not implementation or compliance training.

Branch	Read first	Entry lesson
Coherence	AXI channels; stable cache permissions	States, ownership and maintenance
Memory	Acceptance, queues and bandwidth units	Controller and PHY
PCIe/CXL	Layering, request identity and resources	Requests, links and completions
Peripherals	Register access and sampled events	Serial timing and acknowledgements
High-speed I/O	Layers, payload rates and finite buffering	USB transfer model

By role

RTL owner: fundamentals → AMBA → memory interfaces → debug pages.

Verification owner: fundamentals → protocol verification → AMBA/coherence.

SoC architect: fundamentals → bandwidth budgeting → coherence → PCIe/CXL.

Bring-up engineer: memory interfaces → PCIe/CXL → high-speed I/O → debug.