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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
    • PCIe Layering & TLPs
    • Enumeration & Link Training
    • CXL Attach Modes
    • PCIe / CXL Debug
      • PCIe / CXL Debug: Concepts
      • PCIe / CXL Debug: Integration
      • PCIe / CXL Debug: Debug
      • PCIe / CXL Debug: Interview
    • PCIe & CXL: Tricky Q&A
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←PCIe / CXL Debug
  1. Topics
  2. Bus Protocols
  3. PCIe & CXL
  4. PCIe / CXL Debug
  5. PCIe / CXL Debug: Interview
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    Interface ProtocolsAll levels

    PCIe / CXL Debug: Interview

    Interview for PCIe / CXL Debug.

    Interview drills

    Why is the address alone not enough to match a late Completion after recovery?

    Check yourself Why is the address alone not enough to match a late Completion after recovery?

    Multiple operations may use the same address, and identifiers can later be reused. Retain the request identity and apply the protocol/platform’s recovery policy before recycling tracking.

    Common trap: Giving a generic fix without identifying the boundary and unmet obligation in this example.

    What evidence separates link training failure from firmware enumeration failure?

    Check yourself What evidence separates link training failure from firmware enumeration failure?

    LTSSM history, negotiated parameters and lane diagnostics describe training. Configuration requests/completions, resource assignments and firmware/OS logs describe enumeration. L0 at the expected width is useful evidence, not proof that the transaction path is fault-free; an undiscovered device can involve reset, endpoint responses, routing, permissions or software setup. Compare the first failing operation before assigning ownership.

    Common trap: Treating the final link state or an enumeration log as proof of one owning layer.

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    Up nextPCIe & CXL: Tricky Q&A

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    See also

    • PCIe / CXL Debug: Concepts
    • PCIe / CXL Debug: Integration