Symptom: Device enumerates but DMA timeout. Link x4 Gen4 healthy. AER shows no errors. Driver times out on read.
Separate finite per-link flow-control stalls from requester Tag availability and local reservations for returning completions; apply the port-specific infinite-credit rules.
TLP trace: are MemRd TLPs sent? Are CplD TLPs returned?
Distinguish CPU access to endpoint BAR registers from device DMA to host memory. For host-directed DMA, check the DMA address returned by the platform mapping API, its lifetime, direction and any IOMMU translation/permission; it need not point inside the endpoint BAR.
Check bus-master enable and the actual request size against configured MPS/MRRS, buffer limits and path capabilities; do not require all fields to have identical values at every function.
If CXL: separate .io config from .cache/.mem data path.
Debugging driver before confirming TLP completion.
Ignoring AER correctable error trend.
Confusing enumeration success with data path health.