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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
    • PCIe Layering & TLPs
    • Enumeration & Link Training
    • CXL Attach Modes
    • PCIe / CXL Debug
      • PCIe / CXL Debug: Concepts
      • PCIe / CXL Debug: Integration
      • PCIe / CXL Debug: Debug
      • PCIe / CXL Debug: Interview
    • PCIe & CXL: Tricky Q&A
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←PCIe / CXL Debug
  1. Topics
  2. Bus Protocols
  3. PCIe & CXL
  4. PCIe / CXL Debug
  5. PCIe / CXL Debug: Integration
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    Interface ProtocolsAll levels

    PCIe / CXL Debug: Integration

    Integration for PCIe / CXL Debug.

    Integration in practice

    Keep an error path in the operation record

    Read first: Read the mechanism and worked trace first

    A read times out after occasional recovery events. Retain the request identity and reset/link epoch rather than correlating only its address; another request may later reuse that address.

    Keep an error path in the operation record — decision record

    Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.

    Decision / observation

    Required evidence

    Consequence

    Request outstanding

    Requester/Tag, byte range and issue epoch

    Retain unfinished byte accounting

    Recovery or reset observed

    Protocol/platform cancellation and recovery policy

    Do not guess that old tracking may immediately be reused

    Later Completion arrives

    Identity and applicable epoch policy

    Prevent matching an old result to unrelated new work

    Check yourself Why is the address alone not enough to match a late Completion after recovery?

    Multiple operations may use the same address, and identifiers can later be reused. Retain the request identity and apply the protocol/platform’s recovery policy before recycling tracking.

    System-level PCIe debug artifacts

    Collect once, use across reviews: LTSSM history, per-lane margin, AER counters, TLP trace for failing transaction, config space snapshot, firmware enumeration log.

    • Protocol analyzer at slot level — correlates with driver timeline.

    • Interpret AER severity/status using the selected revision, mask/configuration and platform recovery policy.

    • A high replay rate is link-layer evidence; correlate physical margin, clocks, reset/recovery events, configuration and observation interval before assigning SI.

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    See also

    • PCIe / CXL Debug: Interview