Read first: Read the mechanism and worked trace first
The host can read an assigned device register aperture, but the first DMA fails. A working CPU-to-BAR path proves a different route from device-to-host DMA.
Separate register access from DMA readiness — decision record
Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.
Decision / observation | Required evidence | Consequence |
|---|---|---|
Read BAR register works | Link, resource mapping and that register path | Does not establish a DMA mapping |
DMA descriptor programmed | Valid OS DMA address, length, direction and ownership | CPU virtual addresses are not device DMA addresses |
DMA launched | Bus-master enable, route/permissions and device state | Correlate request and completion/error evidence |
No. Use the platform DMA mapping API and the resulting device address; BAR accessibility does not establish DMA address translation or permissions.
Same endpoint may train x4 Gen4 on eval board but x1 Gen3 on product board. Package routing, via stubs, and connector quality affect per-lane margin. SI/PI team owns this evidence.
Compare LTSSM history between working and failing boards.
Lane reversal and polarity inversion are configured during training.
If a retimer is present, collect its supported diagnostics and segment training evidence; do not model it as a PCIe switch with another enumerated hop.