Suppose a known payload traverses a serial link and later fails an application checksum. “Link up” confirms only the link state it names. It does not prove clean coding, frames, DMA delivery or application ownership.
Replay the same sequence numbers and payload at fixed speed, clocks and conditions. Measure counters over the same interval, retain where each checksum is generated/checked, and change one variable only after locating the earliest available discrepancy.
Choose the first failing boundary before tuning equalisation — worked trace
Illustrative isolated example; not measured silicon behaviour.
Evidence | First plausible boundary to inspect | Next discriminating experiment |
|---|---|---|
PCS block/symbol errors rise | Coding / physical receive path | Correlate lane, mode, reference clock and controlled margin data |
PCS clean; MAC frame check fails | Between checked PCS output and MAC check, or an unobserved earlier error | Compare mode/interface timing and captured frames |
Frames clean; DMA buffer differs | DMA/memory/ownership path | Compare observed accepted bytes with mapped buffer contents |
Buffer correct; application result wrong | Software framing / consumption | Replay the same buffer and ownership sequence |
No. It also changes traffic pressure and timing. Correlate the earliest failing boundary and a controlled setting change before assigning the cause.
High-speed I/O bugs involve silicon (MAC/PHY), board (SI, routing), and software (driver, firmware). Collect PHY margin, MAC counters, and protocol trace in one review.
A package or board-path change requires reviewing which prior SI evidence and assumptions still apply.
Temperature affects PHY margin — test at corners.
Protocol trace and PHY margin are complementary but still need clocks, resets, configuration, counters and traffic context.