Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
      • USB Link & Packet Model: Concepts
      • USB Link & Packet Model: Integration
      • USB Link & Packet Model: Debug
      • USB Link & Packet Model: Interview
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
Loading lesson

←High-Speed I/O (USB / Ethernet / MIPI)
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. USB Link & Packet Model
On this page

    Interface ProtocolsAll levels

    USB Link & Packet Model

    USB is host-driven enumeration, endpoint-based data transfer, and layered link management.

    • 4topics
    • 4lessons

    What you'll learn

    USB is host-driven enumeration, endpoint-based data transfer, and layered link management.

    • In the USB 2.0 examples, the host schedules transactions addressed to device endpoints.

    • USB 2.0: distinguish full-speed frames from high-speed microframes. USB 3.x has its own link mechanisms.

    • Descriptors define device capabilities — firmware must match silicon.

    Connection

    Applies layering and packet concepts to external connectivity.


    Key diagram

    USB 2.0 bulk IN: temporary NAK then data

    USB 2.0 bulk IN: temporary NAK then data. Configured USB 2.0 bulk endpoint example without errors or reset. This is not the isochronous retry model or a USB 3.x link-state diagram.
    Configured USB 2.0 bulk endpoint example without errors or reset. This is not the isochronous retry model or a USB 3.x link-state diagram.
    Check yourself Does the NAK branch advance the expected data toggle?

    No. It transfers no accepted data; the later successful transaction uses the still-expected PID.


    Study this topic

    1. Concepts — rules and mental models

    2. Integration — system contracts

    3. Debug — trace the first divergence

    4. Interview — explain and defend your answer

    PreviousNext: USB Link & Packet Model: Concepts

    Up next

    Up nextUSB Link & Packet Model: Concepts

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug