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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
      • MIPI CSI / DSI Overview: Concepts
      • MIPI CSI / DSI Overview: Integration
      • MIPI CSI / DSI Overview: Debug
      • MIPI CSI / DSI Overview: Interview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←High-Speed I/O (USB / Ethernet / MIPI)
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. MIPI CSI / DSI Overview
On this page

    Interface ProtocolsAll levels

    MIPI CSI / DSI Overview

    MIPI moves camera and display data through high-speed lane bursts with strict timing budgets.

    • 4topics
    • 4lessons

    What you'll learn

    MIPI moves camera and display data through high-speed lane bursts with strict timing budgets.

    • CSI-2: camera serial interface. DSI: display serial interface.

    • This example uses conventional D-PHY clock/data lanes; CSI-2 also has other PHY mappings with different signalling.

    • For the scoped CSI-2 packet model, distinguish header protection, long-packet payload CRC and frame-boundary short packets.

    Connection

    Lane-based high-speed protocol — similar PHY challenges to PCIe/Ethernet.


    Key diagram

    Camera pixels and sensor commands take different paths

    Camera pixels and sensor commands take different paths. Conventional camera example; the control bus follows the sensor contract. It is not a DSI panel packet diagram or a claim that every MIPI endpoint is configured over I2C.
    Conventional camera example; the control bus follows the sensor contract. It is not a DSI panel packet diagram or a claim that every MIPI endpoint is configured over I2C.
    Check yourself Does a successful sensor-control register read prove that the pixel path works?

    No. It exercises the separate control path; CSI-2 packets, lanes, receiver format and downstream data delivery remain to be checked.


    Study this topic

    1. Concepts — rules and mental models

    2. Integration — system contracts

    3. Debug — trace the first divergence

    4. Interview — explain and defend your answer

    PreviousNext: MIPI CSI / DSI Overview: Concepts

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    Up nextMIPI CSI / DSI Overview: Concepts

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    See also

    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • High-Speed I/O Debug