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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←High-Speed I/O (USB / Ethernet / MIPI)
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
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    Interface ProtocolsAll levels

    High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A

    Senior interview and review questions for High-Speed I/O (USB / Ethernet / MIPI).

    Section checkpoint

    Separate packet control, transport capacity and downstream service.

    Try these before opening the explanations. This is a self-assessment, not a stored score or certification.

    Check yourself A USB 2.0 bulk IN returns NAK, then a later attempt returns DATA0 successfully. Did NAK consume data or advance the expected toggle?

    No. The NAK carries no accepted payload and does not advance the expected toggle. This bulk handshake must not be used as an isochronous retry model.

    Check yourself The RAW10 example requires 92.16 Mb/s of active pixels. A one-lane configuration budgets only 80 Mb/s after its assumed reserve. Does it fit? If a larger average budget fits, are frame drops excluded?

    It does not fit that stated planning bound. Even a fitting average budget cannot exclude burst overflow or a long downstream memory-service pause. The reserve is an exercise assumption, not a universal MIPI efficiency.

    Ready to continue when you can produce:

    • USB transfer type/speed and accepted data, not merely token attempts.

    • MAC/pixel payload accounting plus packet overhead and finite-buffer assumptions.

    Section Q&A

    Link up but high CRC/FCS error count — where do you look?

    Check yourself Link up but high CRC/FCS error count — where do you look?

    First define where the counter is generated and whether it covers receive frames, code/block errors or another layer. Correlate lane/PCS status, framing, clocks, resets, configuration, traffic and physical measurements; one CRC/FCS counter does not uniquely locate the corruption.

    Common trap: Declaring an SI or driver root cause from one counter.

    How do you choose an equalisation setting?

    Check yourself How do you choose an equalisation setting?

    Sweep supported settings at stated traffic and operating corners while recording BER/error counts and margin. The response can be multi-dimensional and need not form a symmetric U-shaped curve, so do not assume the geometric centre or maximum setting is optimal.

    Common trap: Inferring a universal curve shape from one one-dimensional sweep.

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    See also

    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview