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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
      • Ethernet MAC / PHY Basics: Concepts
      • Ethernet MAC / PHY Basics: Integration
      • Ethernet MAC / PHY Basics: Debug
      • Ethernet MAC / PHY Basics: Interview
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←High-Speed I/O (USB / Ethernet / MIPI)
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. Ethernet MAC / PHY Basics
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    Interface ProtocolsAll levels

    Ethernet MAC / PHY Basics

    Ethernet splits packet processing (MAC), encoding (PCS), and signaling (PHY) — debug the right layer.

    • 4topics
    • 4lessons

    What you'll learn

    Ethernet splits packet processing (MAC), encoding (PCS), and signaling (PHY) — debug the right layer.

    • MAC: framing, CRC, flow control (pause frames), address filtering.

    • PCS: mode-specific encoding, synchronisation and lane alignment; 10GBASE-R uses 64b/66b.

    • PHY: SerDes, equalization, auto-negotiation.

    Connection

    Compare the idea of layers with PCIe, while retaining Ethernet-specific MAC, PCS and physical-medium roles.


    Key diagram

    PCS is a physical sublayer

    PCS is a physical sublayer. Role-level Ethernet view. The medium and selected PHY mode determine coding, interfaces and other physical sublayers; PCS is not outside every PHY.
    Role-level Ethernet view. The medium and selected PHY mode determine coding, interfaces and other physical sublayers; PCS is not outside every PHY.
    Check yourself Where does the selected mode's block-coding evidence belong?

    At the PCS boundary within the PHY architecture, not at the application payload boundary.


    Study this topic

    1. Concepts — rules and mental models

    2. Integration — system contracts

    3. Debug — trace the first divergence

    4. Interview — explain and defend your answer

    PreviousNext: Ethernet MAC / PHY Basics: Concepts

    Up next

    Up nextEthernet MAC / PHY Basics: Concepts

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    See also

    • USB Link & Packet Model
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug