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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
      • High-Speed I/O Debug: Concepts
      • High-Speed I/O Debug: Integration
      • High-Speed I/O Debug: Debug
      • High-Speed I/O Debug: Interview
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←High-Speed I/O Debug
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. High-Speed I/O Debug
  5. High-Speed I/O Debug: Concepts
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    Interface ProtocolsAll levels

    High-Speed I/O Debug: Concepts

    Concepts for High-Speed I/O Debug.

    Core concepts

    Unified high-speed debug methodology

    Cover link state (up/down, speed, width), error counters, PHY margin, packet/frame evidence and software configuration. The useful order depends on available observation points; preserve the same traffic interval and transaction context instead of treating the list as a verdict hierarchy.

    Narrow physical margin is evidence to investigate, not proof that RTL, clocks or software configuration are correct. Confirm counter definitions, traffic and test duration; compare channel, receiver settings and interface timing with a known-good case. Treat each controlled experiment as evidence for or against a hypothesis.

    Join debug evidence across Ethernet boundaries

    Illustrative Ethernet instance of cross-boundary debugging. Counters and logs must cover the same replay and time interval before they can be correlated.

    Observation point

    Useful evidence

    Question it can help answer

    Software / driver

    Operation trace and sequence IDs

    Was the expected payload queued or consumed?

    MAC / frames

    Packet and FCS counters

    Which observed frames passed or failed the frame check?

    PCS / coding

    Block lock and mode-specific coding counters

    Was synchronisation/coding healthy at this boundary?

    Physical path

    Applicable lane, BER and margin measurements

    Does controlled physical evidence support the channel hypothesis?

    What to notice

    • A clean software trace is not evidence that every intervening representation was checked.

    • A correlation is a lead; use a reduced experiment before declaring which component caused the failure.

    Check yourself If application errors rise without matching MAC frame errors, which other rows still deserve investigation?

    Software/ownership and the observed data-delivery boundaries still matter, and the scope of MAC/PCS/physical counters must be checked. One clean counter does not locate the corruption.

    A throughput drop: which measurement would narrow the cause?

    Observation

    Next correlated evidence

    Do not conclude yet

    USB bulk IN returns NAK repeatedly

    Endpoint readiness, firmware queue and host schedule

    A NAK alone does not prove physical corruption.

    Ethernet MAC reports bad FCS

    PCS/PHY errors plus the MAC-side interface and counter definition

    FCS alone does not locate the corrupting stage.

    CSI-2 frame count falls

    Packet/header/payload errors, FIFO overflow and memory service

    A missing frame alone does not prove insufficient lane rate.

    Lower-rate experiment improves all observed counters

    Same payload validity, revised traffic and unchanged observation window

    Improvement does not isolate SI from reduced queueing pressure.

    Check yourself A camera works when both lane rate and frame rate are reduced. Has the board channel been proved faulty?

    No. That experiment changed electrical stress and offered traffic. Compare matched traffic/service conditions or vary one factor at a time to distinguish physical errors from buffering, scheduling and configuration effects.

    Apply the mechanism

    Continue to the integration exercise

    Then trace a failure

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    See also

    • High-Speed I/O Debug: Debug
    • High-Speed I/O Debug: Interview