Read first: Read the mechanism and worked trace first
An illustrative receive replay sends 1,000 numbered valid frames. The MAC counts 1,000 valid arrivals, the DMA ring reports 990 completed buffers and software consumes 980. Assume counters cover the same interval and no reset or filtering occurred.
Count drops at the boundary where they occur — decision record
Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.
Decision / observation | Required evidence | Consequence |
|---|---|---|
MAC to DMA | 1,000 − 990 = 10 missing from completed buffers | Inspect ring capacity, allocation and DMA/error accounting |
DMA to software | 990 − 980 = 10 not yet consumed | Separate pending work from dropped work |
Application loss claim | Need end-of-run drain and sequence accounting | Do not call all 20 missing software frames wire errors |
No. The MAC counted valid arrivals. Reconcile the DMA and software boundaries, including pending buffers and the drain point, before calling any gap loss.
MAC/PHY partitioning depends on the implementation; a PHY can contain substantial digital PCS logic as well as analogue circuitry. Distinguish the selected MAC-side interface from the medium-facing link. For RGMII, satisfy the documented clock/data skew using the chosen board and internal-delay configuration rather than simply matching all trace lengths.
RGMII: check which endpoint or PCB supplies the required clock delay; avoid missing it or enabling it twice.
SerDes reference clock quality affects BER.
MAC address filtering: promiscuous mode for debug.