For the 10GBASE-R example in IEEE 802.3 Clause 49, 64 payload/control bits are represented in a 66-bit PCS block. The 64/66 coding fraction is about 96.97%; the corresponding serial rate is 10.3125 Gb/s for a 10 Gb/s MAC-side rate. This is a specific mode, not a universal Ethernet coding rule.
The frame-overhead calculation below starts at the MAC rate. Do not subtract 64/66 again from an already stated 10 Gb/s MAC rate; doing so counts the same coding expansion twice. Application throughput then depends on frame size, higher-layer headers, gaps, flow control and actual accepted traffic.
Separate MAC rate, block coding and payload rate — worked trace
Illustrative isolated example; not measured silicon behaviour.
Boundary | Illustrative calculation | Avoid this mistake |
|---|---|---|
PCS serial side | 10.3125 × 64/66 = 10 Gb/s | Calling 10.3125 Gb/s application throughput |
MAC occupied time | Frame, preamble/SFD and required gaps | Treating interpacket time as payload |
Application data | Subtract applicable protocol overhead and measure service | Applying a fixed efficiency unrelated to packet size |
No. The MAC rate is already the decoded side of that expansion. Apply overhead only at the boundary where it has not already been accounted for.
Read first: Specialist course: SerDes and physical-link study
Scope: basic frame accounting from IEEE Std 802.3-2022 Clause 3, with a conventional full-duplex 1 Gb/s example below; 10GBASE-R coding is a separate Clause 49 example. MAC processing includes addressing, type/length, payload and FCS. PAUSE is optional MAC control; IP/TCP checksum offload is an implementation feature, not an inherent Ethernet MAC guarantee.
PCS (Physical Coding Sublayer) handles the selected Ethernet mode's coding and synchronisation. For example, IEEE 802.3 Clause 49 defines 10GBASE-R 64b/66b coding. Do not treat this as the encoding of every 10G-or-faster PHY; the medium, mode and generation matter. Interpret PCS error counters with that mode's definitions.
PCS is part of the PHY architecture, not a layer outside every PHY. Other physical sublayers handle medium attachment and signalling. SerDes, equalisation, auto-negotiation and FEC depend on the selected PHY/mode; do not infer all of them from the word Ethernet.
Put PCS inside the PHY architecture
Role-level Ethernet view. The selected mode determines actual physical sublayers, interfaces and signalling; PCS is not an additional layer outside every PHY.
Boundary | Role | Evidence to interpret there |
|---|---|---|
Application / driver | Queues and consumes payload | Sequence and ownership records |
MAC | Frame handling and FCS | Frame, FCS and drop counters |
PCS within PHY | Selected mode's coding and synchronisation | Block/symbol and synchronisation evidence |
Other PHY / medium-facing path | Mode-specific attachment and signalling | Link and applicable physical-margin evidence |
What to notice
FCS and block/symbol checks observe different representations and boundaries.
A counter's location and definition must be known before assigning the physical channel as the cause.
No. It establishes a failed frame check at the MAC boundary. Correlate PCS, physical, interface and configuration evidence to locate the first observed discrepancy.
Line rate versus Ethernet payload rate
Illustrative back-to-back untagged frames on an otherwise idle full-duplex 1 Gb/s link: six-byte destination, six-byte source, two-byte type/length, four-byte FCS, eight bytes preamble/SFD and twelve byte-times interpacket gap. No VLAN, PAUSE or additional gaps. Payload is MAC client data, not TCP application bytes; coding details are outside this MAC-time calculation.
MAC payload | Frame bytes: payload + 18 | Occupied byte-times: frame + 8 + 12 | Payload fraction / ceiling |
|---|---|---|---|
1,500 bytes | 1,518 | 1,538 | 1,500/1,538 ≈ 97.53%; about 975.3 Mb/s. |
46 bytes | 64 | 84 | 46/84 ≈ 54.76%; about 547.6 Mb/s. |
No. Each occupies 84 byte-times including preamble/SFD and minimum gap in this model, while carrying 46 payload bytes. The payload ceiling is about 547.6 Mb/s before higher-layer overhead or extra idle time. The gap is time, not twelve payload bytes appended to the frame.
An RX FCS/CRC mismatch means the checked frame does not match its checksum. It can direct investigation towards the receive path, but it does not alone prove a wire or board fault: compare PHY/PCS errors, interface timing, MAC configuration and observation boundaries. Likewise, inspect the documented meanings of frame-error and TX-drop counters before assigning causes.
Link up with rising FCS errors warrants correlating MAC, PCS and PHY evidence over the same interval. Electrical margin is one candidate; interface timing, mode/configuration, reset/clock events and the counter's observation point remain candidates too.
Pause frames: receiver telling sender to slow down (flow control).
Frames above the path's standard payload/MTU expectation require compatible endpoint and network-path configuration; state whether a quoted size is payload, MTU or full frame.
PTP timestamping: hardware capture at PHY/MAC boundary.