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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
    • APB & AHB Basics
    • AXI Channels & Transfers
      • AXI Channels & Transfers: Concepts
      • AXI Channels & Transfers: Integration
      • AXI Channels & Transfers: Debug
      • AXI Channels & Transfers: Interview
    • AXI-Lite & AXI-Stream
    • AMBA Integration Debug
    • AMBA Family (APB / AHB / AXI): Tricky Q&A
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←AXI Channels & Transfers
  1. Topics
  2. Bus Protocols
  3. AMBA Family (APB / AHB / AXI)
  4. AXI Channels & Transfers
  5. AXI Channels & Transfers: Interview
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    Interface ProtocolsAll levels

    AXI Channels & Transfers: Interview

    Interview for AXI Channels & Transfers.

    Interview drills

    Why does AXI split reads and writes into separate channels?

    Check yourself Why does AXI split reads and writes into separate channels?

    Each channel has its own handshake, allowing address, data and responses to overlap subject to ordering and available resources. Reads can be outstanding while writes are in flight. Useful throughput improves only when the surrounding buffers, tracking and target service can use that concurrency; separate channels alone do not guarantee progress.

    Common trap: Describing one shared handshake, or promising throughput and progress solely from channel independence.

    What must match between AW and W for a write burst?

    Check yourself What must match between AW and W for a write burst?

    AWLEN+1 must equal accepted W beat count, WLAST marks the final accepted beat, and WSTRB must obey address/size byte-lane rules. AXI4 W has no ID: bursts associate in AW order, without interleaving, even if W is offered or accepted before AW. B follows the AW and final-W handshakes with BID=AWID. Preserve each stalled channel offer through its accepting edge.

    Common trap: Checking only the first W beat.

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    See also

    • AXI Channels & Transfers: Concepts
    • AXI Channels & Transfers: Integration