Explain a peripheral write and a narrow SRAM write without merging the different protocol handshakes.
Try these before opening the explanations. This is a self-assessment, not a stored score or certification.
One write completed, on the final PSEL && PENABLE && PREADY edge. A shared-system unmapped AXI access receives default-target DECERR; an APB target error translated upstream is SLVERR. Waiting alone is neither response.
Only lane 3 is enabled within the permitted two-byte window at lanes 2–3. BVALID still requires both AW and final W acceptance on earlier edges. W-first acceptance can be legal; early B cannot be justified by W alone.
Ready to continue when you can produce:
SETUP, ACCESS-wait and ACCESS-completion observations for one register write.
Accepted AXI address/data/response events and an explicit byte-lane mask.
The address phase and previous data phase overlap. Save address/control only when HREADY permits the active address to advance, then compare returned data with that saved context. During an ordinary wait, B can remain offered while A has not completed.
Common trap: Matching HRDATA to the currently visible HADDR rather than the active data-phase request.
With AWSIZE=1 and AWLEN=0, lanes 2 and 3 form the permitted window. WSTRB=0x0C enables both; 0x08 enables only lane 3. A 64-bit physical bus does not imply eight enabled bytes, and strobes outside the address/size window are invalid.
Common trap: Treating WSTRB as a count of bytes or enabling lanes from zero regardless of address.
Each address, data and response channel has its own handshake, which allows independent acceptance and overlap subject to ordering, buffering and dependency rules. Separation enables concurrency; it does not guarantee that every channel progresses or that throughput improves for every workload.
Common trap: Describing AXI as a single shared bus or assuming independent handshakes guarantee progress.
AWLEN+1 must match the number of accepted W beats, with WLAST on the final beat and WSTRB consistent with the address and transfer size. AXI4 W has no ID: write-data bursts associate in AW request order without interleaving. W can arrive before AW. BVALID must wait until both the address and final data beat have been accepted; BID identifies the corresponding AWID.
Common trap: Inventing a WID or requiring AW to arrive before W.
RID or BID selects an ordering stream; it does not uniquely name one request when that ID has several outstanding. Keep accepted requests in order per source context and ID, then compare each completed response with that queue's head. Transactions with different IDs may have different ordering freedom.
Common trap: Using ID as a unique transaction key or replacing the previous expected item when an ID repeats.
When the endpoint contract needs single-beat, ID-less memory-mapped transfers and the required outstanding/ordering behaviour fits AXI4-Lite. Register blocks are common examples; choose from traffic, latency, concurrency and implementation constraints rather than the peripheral's name alone.
Common trap: Assuming Lite means exactly one transaction may ever be outstanding, or ruling it in/out solely by block type.
ID remap, width conversion, burst splitting, cache attribute propagation, and ordering.
Common trap: Blaming the endpoint master only.