Follow one accepted operation through decode, conversion, clock crossings and completion. A locally clean handshake does not establish that the right register or response was used.
Bridge bugs: ID remap, width conversion, burst splitting, attribute drop.
Address map mismatches cause DECERR or silent wrong-slave routing.
Reset sequencing: masters and slaves must release in compatible order.
Applies everything from AMBA topics to real SoC integration debug.
At the APB completing ACCESS, not at the earlier CPU0 address or data acceptance.
Concepts — Follow CPU0's register write and distinguish decode/target errors.
Integration — State admission, reset and outstanding-work recovery policies.
Debug — Reconcile identity, enabled bytes and crossing events.
Interview — Explain evidence needed at each bridge boundary.