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// Ordinary AXI4 INCR arithmetic on a 64-bit data / 32-bit address interface.
// This is a transfer-shape exercise, not a channel-level AXI implementation.
module tb;
  reg [7:0] memory [0:15];
  integer checks = 0;
  integer expected_count, first_lane;
  reg [7:0] reference_mask;
  reg reference_subset;

  function automatic bit legal_incr(input [31:0] address, input integer size, input integer beats);
    reg [63:0] aligned, last_byte;
    begin
      if (size < 0 || size > 3 || beats < 1 || beats > 256) legal_incr = 0;
      else begin
        aligned = ({32'b0, address} >> size) << size;
        last_byte = aligned + (64'd1 << size) * beats - 1;
        legal_incr = last_byte <= 64'hffff_ffff &&
                     ({32'b0, address} >> 12) == (last_byte >> 12);
      end
    end
  endfunction

  function automatic [7:0] lane_mask(input [31:0] address, input integer size, input integer beat);
    reg [63:0] aligned, current_addr, bus_base;
    integer lower, upper;
    begin
      lane_mask = 0;
      if (size >= 0 && size <= 3 && beat >= 0) begin
        aligned = ({32'b0, address} >> size) << size;
        current_addr = beat == 0 ? {32'b0, address} : aligned + (64'd1 << size) * beat;
        bus_base = (current_addr >> 3) << 3;
        lower = current_addr - bus_base;
        upper = beat == 0 ? aligned + (64'd1 << size) - 1 - bus_base : lower + (1 << size) - 1;
        for (integer lane = 0; lane < 8; lane = lane + 1)
          if (lane >= lower && lane <= upper) lane_mask[lane] = 1;
      end
    end
  endfunction

  function automatic integer bytes_enabled(input [7:0] strobe);
    begin
      bytes_enabled = 0;
      for (integer lane = 0; lane < 8; lane = lane + 1)
        bytes_enabled = bytes_enabled + strobe[lane];
    end
  endfunction

  task require(input bit condition, input string message);
    begin
      checks = checks + 1;
      if (!condition) begin $display("FAIL: %s", message); $finish; end
    end
  endtask

  task apply_beat(input [31:0] address, input integer size, input integer beat,
                  input [63:0] data, input [7:0] strobe);
    reg [63:0] aligned, current_addr, bus_base;
    integer index;
    begin
      require((strobe & ~lane_mask(address, size, beat)) == 0, "strobe outside transfer window");
      aligned = ({32'b0, address} >> size) << size;
      current_addr = beat == 0 ? {32'b0, address} : aligned + (64'd1 << size) * beat;
      bus_base = (current_addr >> 3) << 3;
      for (integer lane = 0; lane < 8; lane = lane + 1) begin
        if (strobe[lane]) begin
          index = bus_base - 64'h2000_0000 + lane;
          require(index >= 0 && index < 16, "exercise memory bounds");
          memory[index] = data[8*lane +: 8];
        end
      end
    end
  endtask

  initial begin
    // Sweep widths, unaligned starts and beats, rather than asserting only one constant mask.
    for (integer size = 0; size <= 3; size = size + 1)
      for (integer offset = 0; offset < 16; offset = offset + 1)
        for (integer beat = 0; beat < 4; beat = beat + 1) begin
          expected_count = beat == 0 ? (1 << size) - offset % (1 << size) : (1 << size);
          first_lane = (beat == 0 ? offset : (offset / (1 << size)) * (1 << size) + beat * (1 << size)) % 8;
          reference_mask = ((1 << expected_count) - 1) << first_lane;
          require(legal_incr(32'h2000_0000 + offset, size, 4), "local four-beat INCR must fit");
          require(bytes_enabled(lane_mask(32'h2000_0000 + offset, size, beat)) ==
                  expected_count,
                  "lane count must match shortened first beat or full subsequent window");
          require(lane_mask(32'h2000_0000 + offset, size, beat) == reference_mask,
                  "lane positions must match independent packed-window construction");
          for (integer mask = 0; mask < 256; mask = mask + 1) begin
            reference_subset = 1;
            for (integer lane = 0; lane < 8; lane = lane + 1)
              if ((mask & (1 << lane)) != 0 && !reference_mask[lane]) reference_subset = 0;
            require(((mask & ~lane_mask(32'h2000_0000 + offset, size, beat)) == 0) ==
                    reference_subset, "strobe subset rule against per-lane reference");
          end
        end

    for (integer size = 0; size <= 3; size = size + 1)
      for (integer offset = 4080; offset < 4096; offset = offset + 1)
        for (integer beats = 1; beats <= 4; beats = beats + 1)
          require(legal_incr(32'h2000_0000 + offset, size, beats) ==
                  (beats <= (4096 - (offset / (1 << size)) * (1 << size)) / (1 << size)),
                  "burst count must fit remaining transfer windows before 4 KiB");

    require(lane_mask(32'h2000_0002, 1, 0) == 8'h0c, "halfword uses lanes 2 and 3");
    require((8'h0f & ~lane_mask(32'h2000_0002, 1, 0)) != 0, "reject enabled lanes outside halfword");
    require(lane_mask(32'h2000_0003, 2, 0) == 8'h08 &&
            lane_mask(32'h2000_0003, 2, 1) == 8'hf0, "unaligned first beat then aligned second beat");
    require(!legal_incr(32'h2000_0ff8, 3, 2), "reject crossing even if strobes are zero");
    require(legal_incr(32'h2000_0ff8, 3, 1) && legal_incr(32'h2000_1000, 3, 1), "both split requests fit");
    require(!legal_incr(32'h2000_0000, 4, 1), "reject size wider than bus");
    require(!legal_incr(32'h2000_0000, 3, 0) && !legal_incr(32'h2000_0000, 3, 257), "reject invalid AXI4 INCR lengths");
    require(!legal_incr(32'hffff_fff8, 3, 2), "detect address-width overflow");
    for (integer i = 0; i < 16; i = i + 1) memory[i] = 0;
    apply_beat(32'h2000_0002, 1, 0, 64'h0000_0000_5aa5_0000, 8'h08);
    require(memory[2] == 0 && memory[3] == 8'h5a, "sparse write preserves disabled byte");
    for (integer i = 0; i < 16; i = i + 1) memory[i] = 0;
    apply_beat(32'h2000_0003, 2, 0, 64'h0000_0000_ab00_0000, 8'h08);
    apply_beat(32'h2000_0003, 2, 1, 64'h8877_6655_0000_0000, 8'hf0);
    require(memory[0] == 0 && memory[1] == 0 && memory[2] == 0 &&
            memory[3] == 8'hab && memory[4] == 8'h55 && memory[5] == 8'h66 &&
            memory[6] == 8'h77 && memory[7] == 8'h88, "unaligned replay byte contents");
    require(checks > 256, "non-zero varied-input work");
    $display("PASS: transfer windows, sparse bytes, unaligned INCR and boundary counterexamples checked");
    $finish;
  end
endmodule

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// Bounded teaching checker for two AXI4 pilot claims; this is not a complete AXI monitor.
// It observes one write at a time and two single-beat reads for one tracked ID.
module axi_pilot_checker #(
  parameter [3:0] TRACK_ID = 4'h3
) (
  input  wire       clk,
  input  wire       rst,
  input  wire       aw_valid,
  input  wire       aw_ready,
  input  wire       w_valid,
  input  wire       w_ready,
  input  wire       w_last,
  input  wire       b_valid,
  input  wire       b_ready,
  input  wire       ar_valid,
  input  wire       ar_ready,
  input  wire [3:0] ar_id,
  input  wire [7:0] ar_tag,
  input  wire       r_valid,
  input  wire       r_ready,
  input  wire       r_last,
  input  wire [3:0] r_id,
  input  wire [7:0] r_tag,
  output reg        premature_b,
  output reg        wrong_same_id,
  output reg        model_capacity_error,
  output reg  [1:0] read_q_count
);
  reg       aw_seen, final_w_seen;
  reg [7:0] read_q0, read_q1;

  wire aw_accept = aw_valid && aw_ready;
  wire w_accept  = w_valid && w_ready;
  wire ar_accept = ar_valid && ar_ready;
  wire r_accept  = r_valid && r_ready;
  wire push_read = ar_accept && ar_id == TRACK_ID;
  wire read_complete = r_accept && r_last && r_id == TRACK_ID;
  wire pop_read = read_complete && read_q_count != 0 && r_tag == read_q0;

  always @(posedge clk) begin
    if (rst) begin
      aw_seen       <= 1'b0;
      final_w_seen  <= 1'b0;
      premature_b   <= 1'b0;
      wrong_same_id <= 1'b0;
      model_capacity_error <= 1'b0;
      read_q_count  <= 2'd0;
      read_q0       <= 8'h00;
      read_q1       <= 8'h00;
    end else begin
      if (aw_accept) aw_seen <= 1'b1;
      if (w_accept && w_last) final_w_seen <= 1'b1;

      // BVALID is an offer. Its prerequisites must have completed on earlier edges.
      if (b_valid && !(aw_seen && final_w_seen)) premature_b <= 1'b1;
      if (b_valid && b_ready) begin
        aw_seen      <= 1'b0;
        final_w_seen <= 1'b0;
      end

      // The response matches the pre-edge head. A new AR on this edge cannot
      // justify a response when the queue was empty before the edge.
      if (read_complete && !pop_read) wrong_same_id <= 1'b1;
      case ({push_read, pop_read})
        2'b10: begin
          if (read_q_count == 0) begin
            read_q0 <= ar_tag;
            read_q_count <= 1;
          end else if (read_q_count == 1) begin
            read_q1 <= ar_tag;
            read_q_count <= 2;
          end else begin
            // Exceeding this observer's capacity is not an AXI violation.
            model_capacity_error <= 1'b1;
          end
        end
        2'b01: begin
          read_q0 <= read_q1;
          read_q_count <= read_q_count - 1'b1;
        end
        2'b11: begin
          if (read_q_count == 1) read_q0 <= ar_tag;
          else begin
            read_q0 <= read_q1;
            read_q1 <= ar_tag;
          end
          // One request enters and one completes: occupancy is unchanged.
        end
        default: begin end
      endcase
    end
  end
endmodule

module tb;
  reg clk = 1'b0;
  always #5 clk = ~clk;

  reg rst;
  reg aw_valid, aw_ready, w_valid, w_ready, w_last, b_valid, b_ready;
  reg ar_valid, ar_ready, r_valid, r_ready, r_last;
  reg [3:0] ar_id, r_id;
  reg [7:0] ar_tag, r_tag;
  wire premature_b, wrong_same_id, model_capacity_error;
  wire [1:0] read_q_count;
  reg saw_premature = 1'b0;
  reg saw_wrong_order = 1'b0;

  axi_pilot_checker dut (.*);

  task idle_inputs;
    begin
      aw_valid = 0; aw_ready = 0; w_valid = 0; w_ready = 0; w_last = 0;
      b_valid = 0; b_ready = 0; ar_valid = 0; ar_ready = 0;
      r_valid = 0; r_ready = 0; r_last = 0;
      ar_id = 0; r_id = 0; ar_tag = 0; r_tag = 0;
    end
  endtask

  task reset_checker;
    begin
      @(negedge clk); idle_inputs(); rst = 1;
      @(negedge clk); rst = 0;
    end
  endtask

  task accept_aw;
    begin
      @(negedge clk); aw_valid = 1; aw_ready = 1;
      @(negedge clk); aw_valid = 0; aw_ready = 0;
    end
  endtask

  task accept_final_w;
    begin
      @(negedge clk); w_valid = 1; w_ready = 1; w_last = 1;
      @(negedge clk); w_valid = 0; w_ready = 0; w_last = 0;
    end
  endtask

  task offer_b;
    begin
      @(negedge clk); b_valid = 1; b_ready = 1;
      @(negedge clk); b_valid = 0; b_ready = 0;
    end
  endtask

  task accept_aw_and_final_w;
    begin
      @(negedge clk);
      aw_valid = 1; aw_ready = 1; w_valid = 1; w_ready = 1; w_last = 1;
      @(negedge clk);
      aw_valid = 0; aw_ready = 0; w_valid = 0; w_ready = 0; w_last = 0;
    end
  endtask

  task accept_ar(input [7:0] tag);
    begin
      @(negedge clk); ar_valid = 1; ar_ready = 1; ar_id = 4'h3; ar_tag = tag;
      @(negedge clk); ar_valid = 0; ar_ready = 0;
    end
  endtask

  task accept_r(input [7:0] tag);
    begin
      @(negedge clk); r_valid = 1; r_ready = 1; r_last = 1; r_id = 4'h3; r_tag = tag;
      @(negedge clk); r_valid = 0; r_ready = 0; r_last = 0;
    end
  endtask

  task exchange_read(input [7:0] completed_tag, input [7:0] new_tag);
    begin
      @(negedge clk);
      ar_valid = 1; ar_ready = 1; ar_id = 4'h3; ar_tag = new_tag;
      r_valid = 1; r_ready = 1; r_last = 1; r_id = 4'h3; r_tag = completed_tag;
      @(negedge clk);
      ar_valid = 0; ar_ready = 0; r_valid = 0; r_ready = 0; r_last = 0;
    end
  endtask

  initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);
    rst = 1;
    idle_inputs();

    // Positive write: early final W, then AW, then B.
    reset_checker();
    accept_final_w();
    accept_aw();
    offer_b();
    if (premature_b) begin
      $display("FAIL: legal W-before-AW write was rejected");
      $finish;
    end

    // Negative write: B is presented after final W but before AW acceptance.
    reset_checker();
    accept_final_w();
    offer_b();
    saw_premature = premature_b;
    if (!saw_premature) begin
      $display("FAIL: premature B was not detected");
      $finish;
    end

    // Positive reads: two requests with ID 3 complete A0 then B1.
    reset_checker();
    accept_ar(8'hA0);
    accept_ar(8'hB1);
    accept_r(8'hA0);
    accept_r(8'hB1);
    if (wrong_same_id || model_capacity_error || read_q_count != 0) begin
      $display("FAIL: legal same-ID completion order was rejected");
      $finish;
    end

    // Positive reads: replace a completed head on the same edge as a new AR.
    reset_checker();
    accept_ar(8'hA0);
    exchange_read(8'hA0, 8'hB1);
    if (wrong_same_id || model_capacity_error || read_q_count != 1) begin
      $display("FAIL: single-entry simultaneous enqueue/dequeue lost occupancy");
      $finish;
    end
    accept_r(8'hB1);
    if (wrong_same_id || read_q_count != 0) begin
      $display("FAIL: replacement request was lost");
      $finish;
    end

    // Positive reads: a full queue can pop and push without exceeding capacity.
    reset_checker();
    accept_ar(8'hA0);
    accept_ar(8'hB1);
    exchange_read(8'hA0, 8'hC2);
    if (wrong_same_id || model_capacity_error || read_q_count != 2) begin
      $display("FAIL: full-queue exchange lost occupancy or reported overflow");
      $finish;
    end
    accept_r(8'hB1);
    accept_r(8'hC2);
    if (wrong_same_id || read_q_count != 0) begin
      $display("FAIL: full-queue exchange changed response order");
      $finish;
    end

    // Observer limit: a third queued request is reported separately from ordering.
    reset_checker();
    accept_ar(8'hA0);
    accept_ar(8'hB1);
    accept_ar(8'hC2);
    if (!model_capacity_error || wrong_same_id || read_q_count != 2) begin
      $display("FAIL: observer capacity limit was confused with AXI ordering");
      $finish;
    end

    // Negative reads: the same requests complete B1 before A0.
    reset_checker();
    accept_ar(8'hA0);
    accept_ar(8'hB1);
    accept_r(8'hB1);
    saw_wrong_order = wrong_same_id;
    if (!saw_wrong_order) begin
      $display("FAIL: wrong same-ID completion order was not detected");
      $finish;
    end

    // Positive write: AW before final W satisfies the same prerequisites.
    reset_checker();
    accept_aw();
    accept_final_w();
    offer_b();
    if (premature_b) begin
      $display("FAIL: legal AW-before-W write was rejected");
      $finish;
    end

    // Positive write: AW and final W can accept at the same edge.
    reset_checker();
    accept_aw_and_final_w();
    offer_b();
    if (premature_b) begin
      $display("FAIL: same-edge AW/final-W acceptance was rejected");
      $finish;
    end

    // Positive write: a legal B offer can remain stalled before completion.
    reset_checker();
    accept_aw_and_final_w();
    @(negedge clk); b_valid = 1; b_ready = 0;
    repeat (2) @(negedge clk);
    if (premature_b || !dut.aw_seen || !dut.final_w_seen) begin
      $display("FAIL: B stall lost accepted write context");
      $finish;
    end
    b_ready = 1;
    @(negedge clk); b_valid = 0; b_ready = 0;
    if (premature_b || dut.aw_seen || dut.final_w_seen) begin
      $display("FAIL: accepted B did not retire write context");
      $finish;
    end

    // Negative write: an illegal B offer is wrong even when BREADY is low.
    reset_checker();
    accept_aw();
    @(negedge clk); b_valid = 1; b_ready = 0;
    @(negedge clk);
    if (!premature_b) begin
      $display("FAIL: B offer without final W was hidden by BREADY=0");
      $finish;
    end
    b_valid = 0;

    // Negative read: an R completion needs an earlier request.
    reset_checker();
    accept_r(8'hA0);
    if (!wrong_same_id || read_q_count != 0) begin
      $display("FAIL: unexpected R response did not report an empty queue");
      $finish;
    end

    // Observer reset policy: abandon tracked work and clear previous flags.
    reset_checker();
    accept_ar(8'hA0);
    accept_aw_and_final_w();
    reset_checker();
    if (read_q_count != 0 || dut.aw_seen || dut.final_w_seen ||
        premature_b || wrong_same_id || model_capacity_error) begin
      $display("FAIL: reset retained observer work or stale failure flags");
      $finish;
    end

    $display("PASS: legal arrivals, stalls and reset passed; response/order faults and observer capacity were detected");
    $finish;
  end
endmodule