Read first: APB completion and AHB address/data association
Read first: AXI channel, byte-window and response contracts
An AXI bridge preserves or explicitly transforms the transaction contract. Width/protocol converters may split one upstream operation into downstream work and must return the correct upstream completion. ID remappers must retain enough source/order context for the upstream rules. An AXI-to-APB converter also serialises unsupported burst/concurrency features according to its documented policy.
An address-map mismatch is a high-value integration hypothesis. Depending on decode and default-target policy, symptoms can include DECERR, another error, a timeout or access to an unintended target; trace the accepted address and route rather than assuming one response.
Maintain a single address map source of truth shared by RTL, firmware, and DV.
Define unmapped-address behaviour explicitly; a responding AXI default target with DECERR improves diagnosis when it fits the system security/safety policy.
Define reset/start-up admission: hold, backpressure or reject requests until the destination path can honour them.
Use the shared model, with SRAM initially zero and both clock domains ready before admission. CPU0 issues one ordinary AXI4 write: ID=1, address=0x4000_0008, AWLEN=0, AWSIZE=2, AWBURST=INCR, AWPROT=000 and AWCACHE=0000. On the 64-bit data bus, WDATA=0x0000_0000_0000_0010 and WSTRB=0x0F enable the four bytes for LEN_BYTES=16. WLAST=1 marks that one data beat.
The bridge retains address and data at their independently accepting clk_sys edges, and stores the correlation key (CPU0, ID 1, sequence 0). Sequence is internal debug/tracking context, not a new AXI or APB signal. The finite request crossing must retain the complete command until the clk_per side can perform it. This exercise's bridge waits for APB completion before producing the upstream B response.
One operation across two clocks
Stages are causal events, not consecutive cycles. clk_sys=100 MHz, clk_per=50 MHz. Crossing latency depends on the implementation; no fixed S-to-P edge offset is assumed.
Stage | Boundary | Evidence | Retained state |
|---|---|---|---|
1 | AXI / clk_sys | AW accepted; W accepted independently | CPU0/ID1/seq0, address, data, strobes, attributes |
2 | Request crossing | Complete command enqueued and delivered once | No loss if the APB side waits |
3 | APB / clk_per | P1: SETUP at 0x4000_0008, PWDATA=0x10, PSTRB=1111 | One selected DMA_CFG command |
4 | APB / clk_per | P2: ACCESS wait; P3: PREADY=1, PSLVERR=0 | LEN_BYTES updates once at P3 |
5 | Response crossing | APB outcome delivered back to clk_sys | Original source/ID/sequence retained |
6 | AXI / clk_sys | BID=1, BRESP=OKAY offered then accepted | Retire this pending write at B acceptance |
What to notice
Four enabled AXI bytes become one full-word APB write; the eight physical AXI lanes do not imply two register writes.
A queued request, APB completion and upstream B acceptance are three different milestones.
No. This request enables only the four bytes at LEN_BYTES. The next address is CONTROL in the model; inventing an enabled write there could change its START bit. Preserve address, transfer size and strobes together rather than splitting by physical width alone.
The shared teaching map routes 0x2000_0000–0x2000_FFFF to SRAM0 and 0x4000_0000–0x4000_FFFF toward APB_BRIDGE. Its default AXI target returns DECERR for an unmapped active request. A routed peripheral access that completes APB with PSLVERR is a different path: the bridge returns SLVERR on the corresponding AXI response. Trace which boundary produced the result rather than diagnosing from an error label alone.
If multiple writes reuse CPU0's ID 1, append them to its pending response queue; BID alone does not select an arbitrary outstanding operation. APB carries no AXI ID, so the bridge keeps the association internally while serialising peripheral work. ID remapping or transaction splitting requires sufficient retained context to reconstruct upstream ordering and completion.
Three outcomes for the same source interface
Observation | Route evidence | Expected outcome in this model |
|---|---|---|
Write to 0x5000_0000 | AXI default target selected; no APB access | BID restored, BRESP=DECERR |
Routed APB write completes with PSLVERR | PSEL/PENABLE/PREADY/PSLVERR sampled high | Corresponding BRESP=SLVERR |
Routed APB access remains PREADY=0 | Selected ACCESS phase is still waiting | No completed APB result yet; investigate service/reset/clock |
No. This model routes an unmapped write to the AXI default target, which returns DECERR without starting APB. Confirm the decode decision and the completed upstream response before assigning a fault.
Keep source, ID, sequence, address, attributes and enabled bytes associated across every conversion.
Default-target DECERR, peripheral SLVERR and an uncompleted access are distinct outcomes.
A reset can lose a response after a side effect occurred; recovery must account for both before retrying.