The base exercise starts quiescent. Each active-low domain reset is asserted asynchronously and released synchronously in its own domain. Before accepting a new operation, the bridge must know that both relevant domains and crossing resources can honour it. Backpressuring admission is compatible with the source presenting and retaining a valid offer; it must not become a circular rule where both sides wait for the other to offer first.
Reset during traffic needs a separate system contract. Define what happens to each accepted request, retained payload, side effect and response if one domain resets. A register write may already have reached the peripheral even if the upstream response was lost. Retrying without knowing that outcome can repeat a side effect. A coordinated drain/reset or explicitly specified failure/recovery policy needs evidence; clearing one local queue is not end-to-end recovery.
No. The write may already have changed the peripheral, and the original requester still expects its completion under the system contract. Recovery must account for accepted work and side effects before permitting a retry or a new epoch of requests.
Before signoff, exercise representative concurrent traffic with production-like initialisation. Trace each applicable bridge transformation—width, ID, burst, address and attributes—and verify clock-domain crossings using a protocol-aware structure whose reset, capacity and backpressure contract has been checked; an asynchronous FIFO is one common implementation, not the only possible architecture.
Place progress/timeout monitoring at useful boundaries with thresholds and recovery defined by system service assumptions; base AXI itself sets no universal response deadline.
Interconnect route table must match firmware memory map.
Power domain crossings need isolation — not just clock domain.