Isolated target contract: seven-bit address 0x50, one-byte register pointer 0x10 and one-byte read result 0xA6. The target preserves that pointer across a repeated START. This is a chosen device contract, not a universal register format imposed by I²C.
During a transmitted byte the sender owns SDA for eight data clocks; the receiver owns the ninth-clock acknowledgement. Open-drain participants release SDA to send high. On the final received byte the controller deliberately NACKs before STOP; that is successful termination, unlike an address NACK.
Walk the acknowledgement owner through a register read — worked trace
Illustrative isolated example; not measured silicon behaviour.
Phase | Byte / event | Who supplies ACK/NACK? |
|---|---|---|
START then address + W | 0xA0 on wire | Target ACKs its address |
Register pointer | 0x10 | Target ACKs the pointer |
Repeated START then address + R | 0xA1 on wire | Target ACKs its address |
Read byte | Target sends 0xA6 | Controller NACKs to end this one-byte read |
STOP | Bus released | No extra data-byte acknowledgement |
After 0xA6 the controller is the receiver and intentionally ends the read. After address byte 0xA1, the target was expected to acknowledge selection; its NACK would prevent this read from starting.
Scope: NXP UM10204 Revision 7.0, Standard-mode/Fast-mode/Fast-mode Plus, using a 7-bit-addressed target. High-speed and Ultra Fast-mode have different restrictions and are outside this example. The sensor register-pointer behaviour below is an explicit target contract, not a requirement imposed on every I²C device.
START condition (SDA falls while SCL high) → 7-bit address + R/W bit → ACK from target → data bytes with ACK/NACK → STOP (SDA rises while SCL high). Each byte is 8 data bits plus ACK bit on the 9th clock.
Open-drain means a device pulls the line low or releases it; the pull-up returns the line high. Resistance and bus capacitance set rise time, while the low-level sink-current and VOL limits bound how strong the pull-up may be. Select the value from the required I²C mode, measured/estimated capacitance and every participant's electrical limits.
One-byte register read: who drives each acknowledgement?
Illustrative target address 0x50, one-byte register pointer 0x10, returned byte 0xA5. Target is powered/ready, supports this combined transfer, and no other controller arbitrates. The seven-bit address is 0x50; wire address bytes are 0xA0 and 0xA1.
Phase | Eight-bit sender / value | Ninth-clock actor |
|---|---|---|
START then address+write | Controller sends 0xA0 | Target drives ACK low. |
Register pointer | Controller sends 0x10 | Target drives ACK low. |
Repeated START then address+read | Controller sends 0xA1 | Target drives ACK low. |
Data | Target sends 0xA5 | Controller releases SDA for NACK: this is the final byte. |
STOP | Controller ends the transfer | No extra acknowledgement byte. |
What to notice
The acknowledgement sender depends on the phase. The controller NACKs the last read byte intentionally.
A repeated START changes direction without a STOP that would end this combined transfer.
No. Here the target acknowledged both address bytes and returned data. The controller intentionally NACKed the final read byte. An address NACK would occur on the ninth clock immediately after an address byte.
During clock stretching, a target can hold SCL low after a controller releases it. A controller that supports stretching observes the actual SCL level before advancing. Any timeout and recovery action are system/controller policies; choose them from the target's documented maximum behaviour rather than assuming an I²C-wide limit.
With multiple controllers, arbitration is performed while SCL is high: a controller that releases SDA but observes it low has lost arbitration and stops driving the transfer as specified. Retry timing and software reporting belong to the controller/platform contract.
Fast mode (400 kHz) and Fast mode Plus (1 MHz) have tighter timing.
Address NACK candidates include no powered/ready target at that address, an address/strap mismatch, or electrical/timing failure; inspect the bus before choosing one.
Repeated START (Sr) for read-after-write without releasing bus.