Protocols stack in four layers, each with a distinct vocabulary and failure mode. The software layer expresses intent: read a register, write a DMA buffer, map a PCIe BAR. The transaction layer encodes that intent into a portable contract — ID, address, burst length, byte enables, cache/shareability attributes, ordering hints, and security/privilege bits.
Use these four views as a debug framework, not identical formal layer names for every interface. AXI uses channel handshakes; PCIe has a transaction layer carrying TLPs and a separate link layer; DDR schedules memory commands through a controller/PHY boundary. Clocks, pins, signalling and training supply physical evidence appropriate to the selected interface.
A software timeout can result from admission, ordering, flow control, reset, power, link or physical failures. Wrong data can come from access width, attributes, ordering, coherency, address translation or a physical integrity fault. Start by defining the failed transaction and observation boundary, then collect evidence at each boundary before proposing a fix.
One STATUS read, four observation boundaries
The course's CPU0 upstream read: ID 1, address 0x4000_0010, four bytes. APB completion and cross-clock handling remain separate downstream events.
View | Evidence for this read | What it does not establish |
|---|---|---|
Software | Read DMA_CFG.STATUS | That hardware has accepted a request |
Transaction | CPU0, ID 1, 0x4000_0010, four bytes | That a response has returned |
Channel | Accepted AR; one accepted R beat with RLAST | Downstream correctness beyond the observed fields |
Sampling | Upstream edges in clk_sys | A cycle-by-cycle timing claim about the APB domain |
What to notice
Carry the same operation through every view; a software timeout is a symptom, not a layer verdict.
Record the observation clock before correlating events across the bridge.
The channel row: accepted R with the expected result and final-beat indication. Software intent and accepted AR alone do not supply returned data.
A transaction is more than address and data. Depending on the protocol, its contract can include cacheability/shareability, access size and strobes, exclusivity or atomic semantics, ordering attributes, privilege and security state. For example, AXI4 AxLOCK marks an exclusive access rather than serving as a general ordering hint; PCIe Relaxed Ordering has its own defined scope.
A bridge that changes an attribute can change the system contract even when both interfaces obey their local handshake rules. Whether that produces stale data, posting differences or an access fault depends on the cache-coherency domain, endpoint behaviour and software contract, so the bridge specification must define every transformation.
Retain the available source port, ID/tag, sequence and request fields; address or numeric ID alone need not identify simultaneous operations.
Attribute set: cache, shareable, bufferable, privilege, security.
Every bridge datasheet must list which fields pass, transform, or drop.
Transaction identity need not remain numerically unchanged across a bridge, but the implementation must preserve an unambiguous mapping between each admitted upstream operation and its downstream work and completion. Useful correlation fields include upstream port plus ID, address range, endpoint/function, byte offset and cache line.
ID remapping, attribute conversion, burst splitting and port merging are integration-risk points. Each may be legal when its mapping, buffering and ordering constraints are explicit; each becomes a bug when the bridge cannot reconstruct the required upstream response or violates an end-to-end contract.
What to notice
The absence of APB ID wires does not erase the upstream response obligation.
Byte, attribute and status transformations need their own documented contract; local handshakes do not verify them.
From retained upstream context. The APB completion supplies status but does not carry CPU0's BID or source-port identity.
Use a symptom table to select the next observation, not to skip to a root cause. A timeout asks where the request last made progress. A protocol assertion identifies the checker, interface, sampled condition and assumptions. Link-down status asks whether configuration, reset, training and electrical prerequisites were met. A mismatch asks whether the two observations used the same address, byte lanes, time and data version.
List the symptom in software-visible terms (timeout, wrong data, hang, corrupt packet).
Identify which interface and which transaction ID is involved.
Walk the path boundary by boundary and record the last confirmed state transition.
Collect the artifact native to that layer (txn log, waveform, LTSSM, training log).
Form competing hypotheses, then change or observe one discriminator at a time.
A captured waveform shows selected signals over a finite interval. Assertions or a checker may establish particular local rules under stated assumptions, but neither establishes every end-to-end attribute, ordering, identity or software requirement.
A VIP result covers the monitored rules, traffic and assumptions at that interface. Chip paths add bridges, maps, initialisation, clocks, resets and power states. System replay adds evidence for that scenario; it is not a proof of every product behaviour.
Layering is a debug partition. Each layer has different owners, artifacts, and fix levers. Mixing layers in a bug review wastes weeks.