A processor address first becomes a controller request, then a bank/row/column selection, then commands scheduled under timing constraints. The PHY handles command/data signalling; it cannot make a controller’s premature command legal. A row hit reuses an open row; a row conflict requires closing one row before opening another.
For this isolated bank example use illustrative tRCD=10, tRP=10, tRAS=24, tRTP=4 and read latency CL=10 controller ticks. These are invented teaching values, not a DDR4 speed bin. Assume a read at the earliest tRCD, no bus conflict, no refresh and no additional constraints relevant to the shown commands.
From a read request to legal DRAM commands — worked trace
Illustrative isolated example; not measured silicon behaviour.
Command / milestone | Earliest tick | Constraint |
|---|---|---|
ACT opens row A | 0 | Bank starts precharged |
READ A | 10 | ACT + tRCD |
First read data | 20 | READ + CL in this simplified exercise |
PRE closes row A | 24 | max(ACT + tRAS, READ + tRTP) = max(24,14) |
ACT opens conflicting row B | 34 | PRE + tRP |
The row must also remain active for tRAS. Both constraints apply; max(24,14)=24 is the earliest PRE tick in this exercise, and the next ACT waits until 34.
Read first: Bandwidth and latency: establish the measurement boundary
Scope: DDR4 command relationships, with all numerical exercise values explicitly illustrative. Device timing limits come from the selected DDR4 part, speed bin, mode and temperature range; they are not interchangeable with LPDDR or newer DDR generations. DFI is a separately versioned controller/PHY interface, not the external DRAM command specification.
The memory controller translates AXI (or similar) requests into DRAM commands: ACTIVATE (open row), READ, WRITE, PRECHARGE (close row), REFRESH. Scheduling policy determines which pending request gets the next command slot.
Row buffer (page) policy: open-page retains an active row for possible later hits. Close-page arranges to close it after an access, subject to legal precharge timing, for example with auto-precharge. Adaptive policies decide from observed or predicted traffic; none is universally best.
What to notice
The controller schedules legal commands against retained bank and timing state.
The PHY's calibration/capture evidence does not prove the command scheduler is legal.
No. The controller's command legality and the PHY's physical capture margin are separate obligations in the figure.
One bank: hit, conflict, then new row
Illustrative bank B initially has row A open. Q0 reads A, Q1 reads B's different row Z. Requests are ordinary reads, no reset/error/refresh intervenes, and the chosen scheduler serves Q0 before Q1. Names A and Z are rows, not addresses in the shared SRAM map. This is command order, not a timed DDR waveform.
Work | Bank action | Required evidence before next action |
|---|---|---|
Q0 hits row A | READ A | Observe the read's command/data relationship and legal timing. |
Q1 conflicts with A | Wait until PRECHARGE is legal; PRECHARGE B | Respect active-row and preceding-access restrictions, not just queue order. |
Bank is closed | Wait tRP; ACTIVATE Z | The selected device's precharge-to-activate interval has elapsed. |
Z is active | Wait tRCD; READ Z | The selected device's activate-to-read interval has elapsed. |
Read data returns | Associate data with Q1 | Use saved request context; a later command may already be on the command bus. |
No. They target different rows of that bank. The controller must close A legally, wait tRP, activate Z and wait tRCD before the column read, as well as meeting the other selected-device timing constraints. This sequence alone does not calculate full AXI latency.
The PHY implements the electrical interface and training used to capture and launch data reliably. For DDR3/DDR4, write levelling adjusts write DQS relative to CK at the DRAM. Read capture and DQ-to-DQS deskew/centring establish different timing relationships. The available calibration, voltage-reference training and tracking steps depend on the selected memory and PHY.
PHY and controller communicate through a defined interface (DFI is common). A command the controller thinks it issued may fail at the PHY if timing margins are insufficient.
DFI interface: controller sends commands, PHY reports readiness and training status.
Multi-rank systems add chip-select and rank-switching overhead.
ECC placement is implementation-specific: establish whether checking and correction sit in a controller, PHY-integrated block, memory device or another datapath stage before interpreting counters.