Start from the failure symptom. Identify the interface. Load waveform with protocol-relevant signals (not every signal in the design). Annotate transaction boundaries using VIP monitor or manual trace.
Scroll backward from the failure to find the earliest observed point where progress stopped or behaviour diverged from the stated expectation. The timeout 1000 cycles later is an observation; the causal dependency may begin earlier or outside the captured boundary.
Response offered versus response accepted
Illustrative single write, AW and final W already accepted; no reset or target error. These rows are constructed teaching observations, not captured simulation output.
Sample | BVALID / BREADY | Accepted B count | Next investigation |
|---|---|---|---|
E1 | 1 / 0 | 0 | Responder has offered status; inspect upstream readiness. |
E2 | 1 / 0 | 0 | Still stalled; retain response payload. |
E3 | 1 / 1 | 1 | Response accepted; correlate retirement at the requester. |
No. BVALID is already high, while the requester has not accepted it. Investigate BREADY, the requester/bridge state and the chosen timeout policy. The table alone does not identify why readiness is low.
Signal grouping: one group per channel (AR, AW, W, R, B for AXI).
Marker: tag the failing transaction's ID and timestamp.
Compare failing vs passing waveform side-by-side.
Waveform shows signals. VIP monitor shows transactions. Firmware log shows software actions. Analyzer shows external protocol view. Align timestamps across all views for the same transaction.
Transaction-only evidence can sometimes establish a semantic mismatch, while a signal trace can establish a local rule violation. Locating the cause across a bridge usually needs both views. Record clock-domain, time origin, reset epoch and correlation mapping before comparing timestamps; do not assume log line order is a global hardware order.
Export VIP monitor to CSV — overlay with waveform markers.
Simulation: $display or transaction recording at key points.
Silicon: logic analyzer on external pins + on-chip trace buffer.