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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Bus Integration Lab
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Protocol Verification & Compliance
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. Protocol Verification & Compliance: Tricky Q&A
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    Interface ProtocolsAll levels

    Protocol Verification & Compliance: Tricky Q&A

    Senior interview and review questions for Protocol Verification & Compliance.

    Section checkpoint

    Produce evidence that the checker detects a meaningful failure without rejecting legal controls.

    Try these before opening the explanations. This is a self-assessment, not a stored score or certification.

    Check yourself W stalls, then its data changes on the accepting edge. A monitor that records only accepted beats sees one valid word. What observation is missing?

    The prior stalled offer. Retention is a relation across sampled edges, including the accepting edge. An accepted-beat-only log cannot establish that the offered payload remained stable.

    Check yourself The teaching harness prints PASS after detecting a planted fault. Is the faulty implementation protocol-compliant, or is the whole course validated?

    Neither. The harness passed its expectation that the checker reject that mutation for the intended reason. Course/source/render gates need their own recorded evidence, and a bounded teaching model never establishes complete AXI or product compliance.

    Ready to continue when you can produce:

    • A requirement/stimulus/checker/result matrix with nonzero work counts.

    • Legal controls, isolated counterexamples, clean repaired replay and recorded limitations.

    Section Q&A

    Scoreboard vs assertion — division of labour?

    Check yourself Scoreboard vs assertion — division of labour?

    Assertions are well suited to precisely sampled temporal and protocol properties; scoreboards model and correlate expected end-to-end results and ordering. Their scopes can overlap, and both depend on assumptions, observation points and reference-model correctness.

    Common trap: Treating either mechanism alone as proof of system correctness.

    What is a compliance gap?

    Check yourself What is a compliance gap?

    An applicable requirement lacks adequate reviewed correctness evidence. A mapped test or hit coverage bin may still be insufficient if no checker observes the required result. Repair the evidence plan or record justified scope/risk disposition; a waiver does not verify the requirement.

    Common trap: Treating a coverage bin or waiver as a passing correctness result.

    VIP pass but chip fails — why?

    Check yourself VIP pass but chip fails — why?

    The results cover different boundaries, configurations or scenarios. Compare actual traffic, map, reset, clocks, bridge transformations, firmware and reference-model assumptions. Those differences guide experiments; they do not establish the faulty component without discriminating evidence.

    Common trap: Closing the bug as 'VIP issue' or assigning integration as the cause without tracing it.

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    See also

    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan