An enabled consistent memory mapping and the OS’s usable region/allocation state, followed by the intended access test—not configuration discovery alone.

Common trap: Giving a generic fix without identifying the boundary and unmet obligation in this example.

CXL.cache: device caches host memory with hardware coherency — device initiates cache transactions to host addresses. CXL.mem: device-attached memory mapped into host address space — host accesses device memory via load/store. Different attach types, different coherency models.

Common trap: Treating all CXL as PCIe DMA.