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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
    • DDR Controller / PHY Split
    • Training & Timing Modes
    • Refresh & Bandwidth Efficiency
    • Memory Interface Debug
    • Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Memory Interfaces (DDR / LPDDR / HBM)
  1. Topics
  2. Bus Protocols
  3. Memory Interfaces (DDR / LPDDR / HBM)
  4. Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A
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    Interface ProtocolsAll levels

    Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A

    Senior interview and review questions for Memory Interfaces (DDR / LPDDR / HBM).

    Section checkpoint

    Distinguish command legality, measured margin and throughput accounting.

    Try these before opening the explanations. This is a self-assessment, not a stored score or certification.

    Check yourself Row A is active, but the next request wants row Z in the same bank. Does READ Z follow immediately, and does a training pass make illegal scheduling safe?

    No. Close A when legal, meet tRP before ACTIVATE Z, then tRCD and other selected-device restrictions before the column access. PHY training cannot repair illegal controller command timing.

    Check yourself In the illustrative one-rank model, refresh occupies 350 ns per 7,800 ns. May you subtract 4.49% refresh and every other reported stall percentage independently from peak?

    No. 350/7,800 is about 4.49% rank occupancy for that schedule. Other ranks can overlap work, and reported causes can overlap in time. Measure accepted useful bytes and classify overlapping constraints without counting the same interval twice.

    Ready to continue when you can produce:

    • A same-bank row-conflict command sequence with selected-device timing references.

    • Margin observations and a refresh occupancy calculation with explicit assumptions.

    Section Q&A

    Why is effective DDR bandwidth below peak?

    Check yourself Why is effective DDR bandwidth below peak?

    Measure useful bytes per elapsed time, then correlate rank availability, bank/row state, command timing, direction changes, queueing and the offered traffic. Refresh occupancy at one rank is not automatically channel-wide bandwidth loss, and reported stall causes can overlap. Use the selected device/mode and avoid subtracting the same interval twice.

    Common trap: Multiplying width×frequency only or adding every reported loss percentage independently.

    What does training establish?

    Check yourself What does training establish?

    It establishes the timing and/or voltage relationships implemented by the selected memory and PHY—for example write DQS-to-CK, DQ-to-DQS capture relationships or a supported voltage threshold. A pass at one condition is not a lifetime or all-corners guarantee.

    Common trap: Calling every training step an eye-centre search or assuming one boot result covers product life.

    Row hit, idle bank, and row conflict — how do they differ?

    Check yourself Row hit, idle bank, and row conflict — how do they differ?

    A hit can issue the column command when timing permits. An idle bank needs ACTIVATE first. A conflict needs PRECHARGE of the active row, then ACTIVATE and the column command. Device timings, scheduler and queueing determine the measured latency.

    Common trap: Calling every non-hit a precharge-plus-activate conflict.

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    See also

    • DDR Controller / PHY Split
    • Training & Timing Modes
    • Refresh & Bandwidth Efficiency