Training & Timing Modes: Interview · protocols

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Why can copying the same timing register counts into a faster clock mode break a working memory system?

Check yourself Why can copying the same timing register counts into a faster clock mode break a working memory system?

A count can represent a shorter physical interval after the clock change. Recompute the cycle/time minima and apply the selected mode’s complete configuration sequence.

Common trap: Giving a generic fix without identifying the boundary and unmet obligation in this example.

What does training establish?

Check yourself What does training establish?

Training establishes the timing and voltage relationships required by the selected memory/PHY. DDR3/DDR4 write levelling adjusts write DQS relative to DRAM CK; data deskew and centring address DQ relative to DQS; voltage-reference training adjusts a supported sampling threshold. These are not all searches for the same eye centre. Validate available margins across the required process, voltage and temperature conditions, and follow the PHY's tracking/recalibration requirements.

Common trap: Assuming training is one-time for life of product.

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