DDR Controller / PHY Split · protocols

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Interface ProtocolsAll levels

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What you'll learn

The memory controller thinks in commands. The PHY thinks in picoseconds. Debug requires both views.

Controller schedules READ/WRITE/REFRESH/ACTIVATE commands to banks.
PHY handles DQS/DQ timing, training, and electrical signaling.
The split means bugs can live in scheduling policy or timing margin.

Connection

Survey of controller/PHY boundaries after the bandwidth lesson. It teaches command and evidence reasoning, not a complete DDR controller or device timing implementation.

Key diagram

A read becomes commands before it becomes pins

A read becomes commands before it becomes pins. The controller chooses legal commands and schedules them; the PHY handles their signalling and capture. A row conflict and a precharged bank need different command work.

The controller chooses legal commands and schedules them; the PHY handles their signalling and capture. A row conflict and a precharged bank need different command work.

Check yourself Can a passing PHY calibration make an illegal controller command schedule safe?

No. Calibration and command timing legality are separate responsibilities.

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