Training & Timing Modes · protocols

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Interface ProtocolsAll levels

4topics
4lessons

What you'll learn

Training is how the PHY finds timing margins that work across voltage, temperature, and process variation.

DDR3/DDR4 write levelling relates DQS to CK; data deskew and centring relate DQ to DQS.
Store margins per corner, not just pass/fail.
Validate operating corners and follow the selected PHY's tracking/recalibration requirements.

Connection

PHY-side complement to controller scheduling. Critical for bring-up engineers.

Key diagram

Passing one tap is not measured margin

Passing one tap is not measured margin. The lesson's sampled tap window is a measurement exercise, not a complete training algorithm or proof across untested corners.

The lesson's sampled tap window is a measurement exercise, not a complete training algorithm or proof across untested corners.

Check yourself Which evidence is lost if only the training PASS bit is kept?

The pass-window boundaries, chosen setting, conditions and distance to failing settings.

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