DDR timing is a set of simultaneous constraints, not one fixed latency to add to every request. tRC constrains same-bank ACT-to-ACT spacing; tRRD and tFAW constrain activation activity across banks; tCCD constrains column-command spacing. The selected device and mode distinguish bank-group cases and required cycle/time minima. Micron’s DDR4 SPD field definitions explicitly distinguish these categories; use actual part timing tables for implementation.
Consider only an illustrative activation limiter: minimum ACT spacing 8 ticks and no more than four ACTs in any 40-tick activation window. Ignore other restrictions for this local calculation. This exercise isolates the scheduling mechanism rather than claiming a complete DRAM command checker.
Read the timing names as constraints on pairs or groups of events — worked trace
Illustrative isolated example; not measured silicon behaviour.
Candidate ACTs | Spacing check | Window check / decision |
|---|---|---|
0, 8, 16, 24 | Every gap is 8 | Four activations admitted |
Fifth at 32 | Gap of 8 passes | Five in the first 40-tick window: reject |
Fifth at 40 | Gap from 24 is 16 | First activation ages out: permitted by these two checks |
The rolling-window constraint considers a group of activations. At tick 32 the spacing check passes but the four-activation window check fails; both must pass.
For DDR3/DDR4, write levelling compensates for the different arrival times of CK and write DQS at a DRAM device. During this training mode, the controller adjusts DQS phase relative to CK and uses feedback from the DRAM on DQ. The objective is the required DQS-to-CK timing relationship, not centring write data in a DQS sampling window. See the DDR3/DDR4 write-levelling explanation in AMD PG150.
DQ-to-DQS deskew and centring are separate data-timing tasks. Read training sets up capture of data returned with DQS; voltage-reference calibration concerns a voltage threshold rather than a clock phase. Names and algorithms vary by PHY, so record the relationship each reported result measures. A pass flag is not a quantified eye margin: retain the available timing/voltage margins and validate the required operating corners.
Name the relationship a training result measured
DDR3/DDR4 teaching relationships; exact algorithms, supported measurements and settings come from the selected memory and PHY.
Task | Relationship | Evidence / limitation |
|---|---|---|
Write levelling | Controller DQS relative to DRAM CK | DRAM feedback on DQ; not normal write-data centring |
Write-data timing | DQ relative to DQS at DRAM capture | Separate data-timing calibration and margin |
Read-data timing | Returned DQ/DQS and PHY capture | Read-capture settings and their measured pass window |
Voltage-reference calibration | Supported receiver threshold | Voltage margin, not a clock-phase measurement |
What to notice
DQ feedback in write levelling has a different role from normal data samples.
A PASS for one row cannot stand in for every other relationship or operating corner.
Write levelling measures DQS-to-CK, while the read-data row concerns returned DQ/DQS capture in the PHY. They test different relationships.
Interpret a measured capture window
Illustrative read-capture sweep on one lane: tested taps 0–31, taps 10–22 pass inclusively, tap 9 and tap 23 fail. Repeat conditions and tap resolution are fixed for this exercise. These are not a device's guaranteed timing limits or a complete PHY training algorithm.
Observation / choice | Calculation | What it establishes |
|---|---|---|
Passing taps | 22 − 10 + 1 = 13 | 13 sampled passing settings, not a continuous eye-width measurement. |
Choose tap 16 | Six tap steps to each sampled passing edge | A centred setting within this measured window. |
Choose tap 11 | One step to low passing edge, eleven to high | It passes here but has less measured low-side margin. |
Different voltage or temperature | Repeat the required measurement | This sweep alone establishes no margin at another corner. |
What to notice
Write levelling and this read-capture sweep measure different relationships; passing one cannot substitute for the other.
Retain lane, rank, conditions, sample count and tap interpretation with the result. A pass flag loses that evidence.
16 is six sampled steps from either passing edge, while 11 is only one step from the low passing edge. That is stronger measured margin for this sweep, not certification across voltage, temperature, ranks or other lanes.
DRAM speed bins (DDR4-3200, LPDDR5-6400) define timing parameters: tRCD, tRP, tRAS, tRFC. Mode registers (MRWs) configure the DRAM chip. Firmware must match MRW settings to the speed bin and board design.
Gear-down mode, DLL-off operation and low-power modes can change timing or re-entry requirements. Follow the selected memory, controller and PHY specifications for any required reconfiguration, training or settling sequence; do not assume every mode transition has the same rule.
Mode register dump is the first artifact in any memory bring-up debug.
Training firmware is part of the protocol contract — version it.
Board skew and package routing affect margins as much as silicon.