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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
    • DDR Controller / PHY Split
    • Training & Timing Modes
    • Refresh & Bandwidth Efficiency
      • Refresh & Bandwidth Efficiency: Concepts
      • Refresh & Bandwidth Efficiency: Integration
      • Refresh & Bandwidth Efficiency: Debug
      • Refresh & Bandwidth Efficiency: Interview
    • Memory Interface Debug
    • Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Refresh & Bandwidth Efficiency
  1. Topics
  2. Bus Protocols
  3. Memory Interfaces (DDR / LPDDR / HBM)
  4. Refresh & Bandwidth Efficiency
  5. Refresh & Bandwidth Efficiency: Interview
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    Interface ProtocolsAll levels

    Refresh & Bandwidth Efficiency: Interview

    Interview for Refresh & Bandwidth Efficiency.

    Interview drills

    Does this pair of counters establish 28% lost application bandwidth?

    Check yourself Does this pair of counters establish 28% lost application bandwidth?

    No. The flags overlap, and their observation boundary is a scheduler cycle count. Measure accepted useful bytes and use the flags to explain service intervals.

    Common trap: Giving a generic fix without identifying the boundary and unmet obligation in this example.

    Row hit vs row miss — which is faster?

    Check yourself Row hit vs row miss — which is faster?

    A row hit usually needs only the column command once its timing constraints permit. An access to an idle bank needs ACTIVATE first. A row conflict needs PRECHARGE of the active row, ACTIVATE of the requested row and then the column command. The latency difference comes from the selected device timings, current bank state, scheduler and queueing; stride, mapping and interleaving influence which case occurs.

    Common trap: Ignoring address interleave and stride.

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    See also

    • Refresh & Bandwidth Efficiency: Concepts
    • Refresh & Bandwidth Efficiency: Integration