Read first: Read the mechanism and worked trace first
In an illustrative 100-cycle observation at one scheduler, 20 cycles are marked waiting and eight of those same cycles also carry a refresh-unavailable indication. The flags overlap; neither is a direct measurement of application payload bytes.
Reconcile counters before subtracting bandwidth losses — decision record
Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.
Decision / observation | Required evidence | Consequence |
|---|---|---|
Waiting counter | 20 of 100 cycles | Includes the eight refresh-marked cycles |
Refresh flag | 8 of 100 cycles | Subset of waiting here, not eight additional lost cycles |
Naive sum | 20% + 8% = 28% | Double-counts overlap; the union is 20% in this recorded example |
No. The flags overlap, and their observation boundary is a scheduler cycle count. Measure accepted useful bytes and use the flags to explain service intervals.
Firmware and software can influence DRAM efficiency through allocation, alignment, access order and channel/bank mapping. Huge pages can reduce translation pressure, but they do not by themselves guarantee a higher DRAM row-hit rate; that depends on physical placement, controller mapping and the workload's access sequence.
Set QoS from actual latency/throughput requirements, not agent names: a display DMA can have a harder deadline than a CPU background task. State arbitration and finite-service assumptions so a preferred class cannot silently starve another.
Profile row-hit, idle-bank and conflict rates per traffic class, then interpret them with the address map and latency objective.
Video frame buffers: stride matters for bank mapping.
Low-power and refresh settings can change availability and latency; quantify the effect for the selected mode rather than assuming a fixed bandwidth loss.