Read first: Read the mechanism and worked trace first
Isolated mapping exercise: for 64-byte-aligned addresses, bank=(address>>6)&1 and row=address>>7. Start with every bank precharged. This mapping is invented for the exercise; the real controller may hash or interleave addresses differently.
Check address mapping with a deliberately small bank model — decision record
Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.
Decision / observation | Required evidence | Consequence |
|---|---|---|
0x0000 then 0x0040 | Bank 0 row 0; bank 1 row 0 | Different banks; not a same-bank row conflict |
0x0000 then 0x0080 | Bank 0 row 0 then row 1 | Same bank, different row; resolve existing open-row state |
Repeated 0x0000 with row 0 still open | Same bank and row | Potential row hit, subject to all timing/resource constraints |
No. Under this explicit mapping they select different banks. Decode the actual controller mapping before explaining locality or conflicts.
Place controller near PHY physically — long routes between them add latency and timing risk. Address mapping (which AXI address maps to which rank/bank/row) affects performance as much as scheduler policy.
Multiple ports into one controller need arbitration. CPU, GPU, and display DMA competing for the same DRAM channel need QoS in the controller.
Choose channel/bank interleaving for the workload and service objective; sequential striping is a policy choice, not a universal rule.
ECC scrub interacts with refresh — both steal bandwidth.
Low-power modes (self-refresh) need firmware sequencing with controller.