Read first: Read the mechanism and worked trace first
Illustrative RAW10 line: 1,920 active pixels make 2,400 payload bytes. Assume two data lanes, each at 400 Mb/s, with an explicitly chosen 50 µs budget for this line’s payload plus all overhead. These are teaching assumptions, not a camera mode specification.
Check line-time capacity, not just frame-average rate — decision record
Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.
Decision / observation | Required evidence | Consequence |
|---|---|---|
Aggregate lane rate | 2 × 400 Mb/s = 800 Mb/s | 100 MB/s before overhead |
Payload transfer time | 2,400 / 100,000,000 = 24 µs | 26 µs remains in the stated line budget |
Remaining work | Headers/CRC, transitions and other defined occupancy | Must fit the remaining budget and receiver constraints |
No. It establishes remaining budget, not the actual overhead. Account for packet/physical occupancy and required gaps before approving the mode.
Sensor output format must match CSI-2 receiver config (data type, lane count, speed). Display timing (resolution, refresh, blanking) must match DSI host config and panel spec.
D-PHY and C-PHY use different signalling; confirm the actual PHY or combo-PHY capabilities at both ends.
If a product shares a physical block between camera and display roles, verify its supported mode and ownership restrictions; sharing is not a protocol requirement.
Camera sensors commonly use a separate control bus such as I²C. A DSI panel may receive Display Command Set (DCS) or generic commands over DSI; any additional I²C/SPI control path is panel-specific, not a DSI requirement.