Illustrative level-sensitive interrupt: a receive source stays asserted while FIFO occupancy is above its documented threshold. A write to an interrupt-controller acknowledgement register retires controller state but does not drain the peripheral FIFO.
The handler must service the documented peripheral cause and then complete controller handling in the platform-prescribed order. Do not replace this rule with “always clear status first”: read-to-clear, write-one-to-clear and level conditions differ by peripheral.
Turn a repeated interrupt into a source-to-handler trace — worked trace
Illustrative isolated example; not measured silicon behaviour.
Event | Peripheral source | Controller / software |
|---|---|---|
FIFO crosses threshold | Asserted | Interrupt becomes pending |
Handler acknowledges controller only | Still asserted | Another delivery can occur |
Handler drains below threshold | Deasserts under this chosen source policy | Controller can finish without the same active cause |
New input raises occupancy again | Asserted again | A new interrupt is legitimate |
Its level source is still active. The acknowledgement did not service the peripheral condition; inspect the peripheral’s actual deassertion rule.
Before closing peripheral integration: register R/W test (every field), interrupt test (every source), DMA loopback, reset sequencing with dependent blocks, clock gating verification.
Power domain: peripheral in gated domain needs wake before access.
Pin mux: GPIO function vs peripheral function selection.
Device tree / ACPI tables must match hardware address and IRQ.