Every peripheral has a contract: register map (offsets, reset values, access width), interrupt spec (level/edge, polarity, clear mechanism), clock/reset requirements, and DMA interface (if any). Firmware, RTL, and verification must share one source of truth.
Possible integration mismatches include differing register offsets, a level source configured as an edge interrupt, or DMA starting before the required clock/reset/power state is ready. A working ID register covers only one access, not the serial pins, data path or interrupt route.
Completion status versus interrupt acknowledgement
Use DMA_CFG in the shared address map. For this exercise only, assume IRQ_STATUS.DONE bit 0 is a sticky, enabled level-interrupt source; no new completion occurs during service. IRQ_STATUS at 0x4000_0014 is write-one-to-clear. Interrupt-controller acknowledge/end-of-interrupt operations follow that controller's own contract.
Step | Operation / observation | Source after step |
|---|---|---|
DMA completes | IRQ_STATUS.DONE becomes 1 | Interrupt level asserted under the assumed enable policy. |
CPU acknowledges controller | ISR begins | DONE remains 1; controller acknowledgement did not clear this register. |
ISR inspects status | Confirm this DMA source, retain completion evidence | DONE remains 1 until the clear is accepted. |
ISR writes 0x1 to IRQ_STATUS | W1C accepted at DMA_CFG, with required platform ordering | DONE becomes 0; source level deasserts under the no-new-event assumption. |
ISR finishes controller protocol | Required end-of-interrupt / return | No repeated interrupt from this cleared event. |
Neither clears this assumed sticky source. W1C requires writing a 1 to DONE. The driver must also follow its interrupt-controller protocol and account for new events; this exercise excludes a simultaneous new completion rather than inventing a set/clear priority.
Register spec is the contract — version it with RTL and driver.
Audit reset values against the documented safe state; a correctly disabled peripheral need not transfer data before firmware configures it.
For a persistent level interrupt, distinguish the peripheral source from interrupt-controller pending/active state; acknowledging the controller need not remove the peripheral condition.