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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
    • I2C Timing & Arbitration
      • I2C Timing & Arbitration: Concepts
      • I2C Timing & Arbitration: Integration
      • I2C Timing & Arbitration: Debug
      • I2C Timing & Arbitration: Interview
    • SPI Modes & Chip-Select Rules
    • UART Flow Control
    • Peripheral Integration Debug
    • Embedded Peripherals (I2C / SPI / UART): Tricky Q&A
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Embedded Peripherals (I2C / SPI / UART)
  1. Topics
  2. Bus Protocols
  3. Embedded Peripherals (I2C / SPI / UART)
  4. I2C Timing & Arbitration
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    Interface ProtocolsAll levels

    I2C Timing & Arbitration

    I2C is two wires, open-drain, and deceptively simple — timing violations cause silent failures.

    • 4topics
    • 4lessons

    What you'll learn

    I2C is two wires, open-drain, and deceptively simple — timing violations cause silent failures.

    • Open-drain: SDA and SCL pulled high, devices pull low. Pull-up resistor sizing matters.

    • START/STOP conditions, ACK/NACK, 7-bit or 10-bit addressing.

    • Clock stretching and multi-controller arbitration require explicit controller support and timeout policy.

    Connection

    Simplest serial protocol — illustrates timing contracts between RTL, board, and firmware.


    Key diagram

    One-byte combined register read

    One-byte combined register read. Chosen target contract with one-byte register pointer and one-byte result. ACK ownership changes when the controller becomes the data receiver.
    Chosen target contract with one-byte register pointer and one-byte result. ACK ownership changes when the controller becomes the data receiver.
    Check yourself Who produces the final data-byte NACK in this successful read?

    The controller, because it is receiving the final byte and intentionally ends the read.


    Study this topic

    1. Concepts — rules and mental models

    2. Integration — system contracts

    3. Debug — trace the first divergence

    4. Interview — explain and defend your answer

    PreviousNext: I2C Timing & Arbitration: Concepts

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    Up nextI2C Timing & Arbitration: Concepts

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    See also

    • SPI Modes & Chip-Select Rules
    • UART Flow Control
    • Peripheral Integration Debug